公开(公告)号：US20240096824A1

公开(公告)日：2024-03-21

申请号：US18523320

申请日：2023-11-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Satoshi GOTO ,  Takayuki TSUTSUI ,  Shinnosuke TAKAHASHI

IPC: H01L23/66 ,  H01L25/065 ,  H03F1/56 ,  H03F3/195 ,  H03F3/24

CPC classification number: H01L23/66 ,  H01L25/0657 ,  H03F1/565 ,  H03F3/195 ,  H03F3/245 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2225/06503

Abstract: A stacked semiconductor device capable of increasing heat dissipation comprises a first member and a second member. The first member includes a semiconductor substrate and a first electronic circuit. The first electronic circuit includes a semiconductor element provided on one surface of the semiconductor substrate. A second member is attached to a first surface, which is one surface of the first member. The second member includes a second electronic circuit including another semiconductor element. The second member is provided with a first opening that penetrates the second member in a thickness direction. A first conductor projection is coupled to the first electronic circuit. The first conductor projection protrudes from the first surface of the first member through the first opening of the second member to the outside of the first opening.

公开(公告)号：US20210194444A1

公开(公告)日：2021-06-24

申请号：US17123230

申请日：2020-12-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Kiichiro TAKENAKA ,  Satoshi TANAKA ,  Takayuki TSUTSUI

IPC: H03F3/213 ,  H03F1/56 ,  H05K1/18 ,  H01L23/66 ,  H01L23/00

Abstract: A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.

公开(公告)号：US20200382083A1

公开(公告)日：2020-12-03

申请号：US16995902

申请日：2020-08-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Satoshi TANAKA ,  Takayuki TSUTSUI ,  Yasunari UMEMOTO

IPC: H03F3/21 ,  H03F3/19 ,  H03F1/56 ,  H03F1/02 ,  H01L27/06 ,  H01L21/8252

Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted.

公开(公告)号：US20200161265A1

公开(公告)日：2020-05-21

申请号：US16751899

申请日：2020-01-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Masayuki AOIKE ,  Takayuki TSUTSUI

IPC: H01L23/00 ,  H01L27/082 ,  H01L29/737 ,  H01L29/205 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8222 ,  H01L21/8234

Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

公开(公告)号：US20200154368A1

公开(公告)日：2020-05-14

申请号：US16744852

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi TANAKA ,  Kiichiro TAKENAKA ,  Takayuki TSUTSUI ,  Taizo YAMAWAKI ,  Shun IMAI

IPC: H04W52/24 ,  H03F3/21 ,  H03F1/02 ,  H03F3/19 ,  H04W52/02 ,  H04B1/04 ,  H03F3/24 ,  H03F3/189

Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.

公开(公告)号：US20200052663A1

公开(公告)日：2020-02-13

申请号：US16527578

申请日：2019-07-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Yasunari UMEMOTO ,  Yuichi SAITO ,  Isao OBU ,  Takayuki TSUTSUI

IPC: H03F3/21 ,  H01L23/498 ,  H01F17/00 ,  H01L23/00 ,  H01L23/552 ,  H03F3/213 ,  H03F1/02 ,  H01L23/66

Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

公开(公告)号：US20190356288A1

公开(公告)日：2019-11-21

申请号：US16382324

申请日：2019-04-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takayuki TSUTSUI ,  Masao KONDO ,  Satoshi TANAKA

IPC: H03F3/24 ,  H03F3/19 ,  H03F3/21

Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases.

公开(公告)号：US20190326191A1

公开(公告)日：2019-10-24

申请号：US16374674

申请日：2019-04-03

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Isao OBU ,  Yasunari UMEMOTO ,  Yasuhisa YAMAMOTO ,  Masahiro SHIBATA ,  Takayuki TSUTSUI

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H03F1/30

Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.

公开(公告)号：US20190190455A1

公开(公告)日：2019-06-20

申请号：US16223300

申请日：2018-12-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Satoshi TANAKA ,  Yasuhisa YAMAMOTO ,  Takayuki TSUTSUI ,  Isao OBU

IPC: H03F1/02 ,  H03F3/19 ,  H03G3/30 ,  H03F3/24

CPC classification number: H03F1/0211 ,  H03F3/19 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/21103 ,  H03F2203/21139 ,  H03G3/3042 ,  H03G2201/106

Abstract: A transmission unit includes a first transistor that amplifies power of a first signal and outputs a second signal, a power supply circuit that supplies to the first transistor a power supply voltage that changes in accordance with an amplitude level of the first signal, and an attenuator that attenuates the first signal in such a manner that an amount of attenuation of the first signal increases with a decrease in the power supply voltage when the power supply voltage is less than a first level.

公开(公告)号：US20190172807A1

公开(公告)日：2019-06-06

申请号：US16210614

申请日：2018-12-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Masayuki AOIKE ,  Takayuki TSUTSUI

IPC: H01L23/00 ,  H01L27/082 ,  H01L27/088 ,  H01L29/165 ,  H01L29/205 ,  H01L29/737

Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.