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114 条记录 (耗时 0.044 秒)

    Magnetic memory device and method of fabricating the same
    61.
    发明授权
    Magnetic memory device and method of fabricating the same 失效
    磁记忆装置及其制造方法

    公开(公告)号：US08043869B2

    公开(公告)日：2011-10-25

    申请号：US12915335

    申请日：2010-10-29

    申请人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

    发明人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

    IPC分类号： H01L29/82

    CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

    摘要翻译： 磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体， 写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

    Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods
    62.
    发明授权
    Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods 有权
    电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法

    公开(公告)号：US07843715B2

    公开(公告)日：2010-11-30

    申请号：US12015624

    申请日：2008-01-17

    申请人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    发明人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/72

    摘要： A memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods are provided. The memory cell of a resistive semiconductor memory device includes a twin cell, wherein the twin cell stores data values representing one bit of data. The twin cell includes a main unit cell connected to a main bit line and a word line, and a sub unit cell connected to a sub bit line and the word line. Also, the main unit cell includes a first variable resistor and a first diode, and the sub unit cell includes a second variable resistor and a second diode.

    摘要翻译： 提供了电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法。 电阻半导体存储器件的存储单元包括双胞胎，其中双胞胎存储表示一位数据的数据值。 双胞胎单元包括连接到主位线和字线的主单元，以及连接到子位线和字线的子单元。 此外，主单元包括第一可变电阻器和第一二极管，并且子单元电池包括第二可变电阻器和第二二极管。

    Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof
    64.
    发明授权
    Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof 有权
    具有三维堆叠和字线解码方法的电阻半导体存储器件

    公开(公告)号：US07808811B2

    公开(公告)日：2010-10-05

    申请号：US12020237

    申请日：2008-01-25

    申请人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    发明人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

    摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.

    摘要翻译： 提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。 在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线 层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由 预定数量的子字线。 可以实现足够高集成度的有效的字线解码。

    MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE
    65.
    发明申请
    MEMORY CELL ARRAY BIASING METHOD AND A SEMICONDUCTOR MEMORY DEVICE 有权
    存储单元阵列偏移方法和半导体存储器件

    公开(公告)号：US20100246248A1

    公开(公告)日：2010-09-30

    申请号：US12732990

    申请日：2010-03-26

    申请人： BEAK-HYUNG CHO ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： BEAK-HYUNG CHO ,  Do-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C11/00 ,  G11C8/08

    CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.

    摘要翻译： 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到 多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路，用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。

    Phase change memory device generating program current and method thereof
    69.
    发明申请
    Phase change memory device generating program current and method thereof 有权
    相变存储器件产生程序电流及其方法

    公开(公告)号：US20100110781A1

    公开(公告)日：2010-05-06

    申请号：US12654338

    申请日：2009-12-17

    申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C17/16

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

    摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

    Bias voltage generator and method generating bias voltage for semiconductor memory device
    70.
    发明授权
    Bias voltage generator and method generating bias voltage for semiconductor memory device 有权
    用于半导体存储器件的偏置电压发生器和产生偏置电压的方法

    公开(公告)号：US07548467B2

    公开(公告)日：2009-06-16

    申请号：US11955562

    申请日：2007-12-13

    申请人： Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    发明人： Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC分类号： G11C5/14

    CPC分类号： G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

    摘要： There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

    摘要翻译： 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。