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725 条记录 (耗时 0.043 秒)

    Carrier leak reduction transmitter circuit
    61.
    发明授权
    Carrier leak reduction transmitter circuit 有权
    载波泄漏减少发射机电路

    公开(公告)号：US07606323B2

    公开(公告)日：2009-10-20

    申请号：US11334571

    申请日：2006-01-19

    申请人： Satoshi Tanaka ,  Yukinori Akamine

    发明人： Satoshi Tanaka ,  Yukinori Akamine

    IPC分类号： H04K1/02

    CPC分类号： H04B1/0475

    摘要： A transmitter circuit has two mixers that modulate a carrier wave according to an input signal, outputs a signal having information in a phase and an amplitude, detects a DC offset in each of the mixers, and adds a DC voltage that corrects the detected DC offset to the input signal of the mixers. The mixer is a double balanced mixer having two load resistors, and the transmitter circuit has a resistor that is connected between a node of two load resistors and a power supply, a limiter amplifier that amplifies a signal, and a control unit that changes first and second potentials using a signal that is outputted by the limiter amplifier. The first and second potentials become a potential of the DC voltage that corrects the DC offset.

    摘要翻译： 发射机电路具有根据输入信号调制载波的两个混频器，输出具有相位和振幅信息的信号，检测每个混频器中的直流偏移量，并加上校正检测到的直流偏移的直流电压 到混频器的输入信号。 混频器是具有两个负载电阻器的双平衡混频器，并且发射机电路具有连接在两个负载电阻器的节点和电源之间的电阻器，放大信号的限幅放大器和首先改变的控制单元 使用由限幅放大器输出的信号的第二电位。 第一和第二电位成为修正直流偏移的直流电压的电位。

    Manufacturing method of semiconductor device
    62.
    发明授权
    Manufacturing method of semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US07509623B2

    公开(公告)日：2009-03-24

    申请号：US11381262

    申请日：2006-05-02

    申请人： Sachiko Kobayasi ,  Toshiba Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

    发明人： Sachiko Kobayasi ,  Toshiba Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

    IPC分类号： G06F17/50 ,  G03F1/00 ,  G03F7/00

    CPC分类号： G03F1/36 ,  G03F7/70441

    摘要： A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

    摘要翻译： 由计算机执行的图案校正方法包括第一校正和第二校正。 对于构成设计图案的边缘中满足条件的边缘（第一边缘），考虑光学邻近效应来计算校正值来执行第一校正。 随后，对于不符合条件的边缘（第二边缘），通过使用与第一边缘相邻的边缘（第一边缘）中的任何一个边缘（第一边缘）的第一边缘的第一边缘 执行校正，从而将校正的第一边缘和校正的第二边缘连接到线段。 该图案被校正为适于掩模绘图和具有简单处理的检查的形状。

    Sigma delta (ΣΔ) transmitter circuits and transceiver using the same
    65.
    发明授权
    Sigma delta (ΣΔ) transmitter circuits and transceiver using the same 失效
    Sigma delta（SigmaDelta）发射机电路和收发器使用相同

    公开(公告)号：US07426377B2

    公开(公告)日：2008-09-16

    申请号：US11207003

    申请日：2005-08-19

    申请人： Satoshi Tanaka ,  Kazuyuki Hori ,  Manabu Kawabe ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

    发明人： Satoshi Tanaka ,  Kazuyuki Hori ,  Manabu Kawabe ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

    IPC分类号： H04B1/06

    CPC分类号： H04B1/406 ,  H04B1/0003

    摘要： A ΣΔ transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90°, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.

    摘要翻译： 即使在多个频带中工作的情况下，也可以将环路滤波器LF，电荷泵电流和其他因素设定为相同条件的SigmaDelta发送器，因此允许减少部件的数量，并且同时启用 要提供用于接收的本地信号的相位之间的角度接近正好90°，这是确保对元件间变化的鲁棒性并因此适合于大规模集成的特征。 将VCO的振荡频率设定为发送频率的偶数倍，经由分频器生成发送信号。 根据调制信号的幅度分量来改变增益的装置被添加到其输入是来自VCO的信号的放大器，并且由此使得涉及幅度调制（例如EDGE）的调制信号的传输成为可能。

    Power control circuit, semiconductor device and transceiver circuit using the same
    66.
    发明授权
    Power control circuit, semiconductor device and transceiver circuit using the same 有权
    电源控制电路，半导体器件和收发电路使用相同

    公开(公告)号：US07415254B2

    公开(公告)日：2008-08-19

    申请号：US11272917

    申请日：2005-11-15

    申请人： Akira Kuriyama ,  Satoshi Tanaka

    发明人： Akira Kuriyama ,  Satoshi Tanaka

    IPC分类号： H04B1/04 ,  H01Q11/12

    CPC分类号： H03G3/3047 ,  H03G3/02 ,  H03G3/3042

    摘要： There is provided a power control circuit having a stable high-speed operation, and a semiconductor device and a transceiver circuit using it. The power control circuit controls the gain of an amplifier so that power outputted from the amplifier reaches a desired value according to a digital control signal. The power control circuit includes a digital feedback loop which converts a detected signal obtained by detecting a value of the output power of the amplifier to a digital signal, determines a differential between the digital signal and the digital control signal, converts the differential to an analog signal and outputs a first feedback signal, an analog feedback loop which outputs a high frequency element corresponding to a differential between an analog signal to which the digital control signal is converted and the detected signal, as a second feedback signal, and an adder which determines the sum of the first and the second feedback signal and outputs a gain control signal for controlling the gain of the amplifier.

    摘要翻译： 提供了具有稳定的高速操作的功率控制电路，以及使用它的半导体器件和收发器电路。 功率控制电路控制放大器的增益，使得从放大器输出的功率根据数字控制信号达到期望值。 功率控制电路包括数字反馈回路，其将通过将放大器的输出功率的值检测到的检测信号转换为数字信号，确定数字信号和数字控制信号之间的差分，将差分转换为模拟 信号并输出​​第一反馈信号，模拟反馈回路，其输出对应于转换数字控制信号的模拟信号与检测信号之间的差分的高频元件作为第二反馈信号，以及加法器，其确定 第一和第二反馈信号的和，并输出用于控制放大器的增益的增益控制信号。

    Semiconductor integrated circuit device
    67.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07414821B2

    公开(公告)日：2008-08-19

    申请号：US11898946

    申请日：2007-09-18

    申请人： Kumiko Takikawa ,  Satoshi Tanaka ,  Masumi Kasahara

    发明人： Kumiko Takikawa ,  Satoshi Tanaka ,  Masumi Kasahara

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H03F1/52 ,  H03F2200/372

    摘要： Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.

    摘要翻译： 在内部电路中工作在高频带内，结合有多级连接的保护电路，其被构造为包括具有低寄生电容并且没有故障的多个二极管连接的晶体管，即使当输入信号 高于施加电源电压。 在内部电路中工作在低频带，其中包括一个保护电路，其构造为包括一个二极管连接的晶体管。 保护电路包括两条保护电路，其中电流方向相反，以保护内部电路免受正/负静电。

    Fabrication of semiconductor device for flash memory with increased select gate width
    70.
    发明授权
    Fabrication of semiconductor device for flash memory with increased select gate width 有权
    具有增加选择栅极宽度的闪存半导体器件制造

    公开(公告)号：US07365018B2

    公开(公告)日：2008-04-29

    申请号：US11319895

    申请日：2005-12-28

    申请人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

    发明人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

    IPC分类号： H01L21/302

    CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

    摘要翻译： 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。 在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以形成 类似的最终结构。