公开(公告)号：US08513084B2

公开(公告)日：2013-08-20

申请号：US12967268

申请日：2010-12-14

申请人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

发明人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC分类号： H01L21/331

CPC分类号： H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

摘要： Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

摘要翻译： 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

公开(公告)号：US20130207235A1

公开(公告)日：2013-08-15

申请号：US13371605

申请日：2012-02-13

申请人： Margaret A. Faucher ,  Paula M. Fisher ,  Thomas H. Gabert ,  Joseph P. Hasselbach ,  Qizhi Liu ,  Glenn C. MacDougall

发明人： Margaret A. Faucher ,  Paula M. Fisher ,  Thomas H. Gabert ,  Joseph P. Hasselbach ,  Qizhi Liu ,  Glenn C. MacDougall

IPC分类号： H01L21/331 ,  H01L29/73 ,  B82Y99/00

CPC分类号： H01L29/732 ,  H01L21/76221 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/737 ,  H01L29/7371

摘要： Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.

公开(公告)号：US20130187198A1

公开(公告)日：2013-07-25

申请号：US13358180

申请日：2012-01-25

申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。

公开(公告)号：US08445967B2

公开(公告)日：2013-05-21

申请号：US13534462

申请日：2012-06-27

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L21/70

CPC分类号： H01L29/127 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7606 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

摘要翻译： 半导体器件包括具有至少一个电掺杂剂原子并由包括至少一个电介质材料层的电介质材料包封的半导体岛。 所述至少一个电介质材料层的至少两部分具有小于2nm的厚度以实现量子隧道效应。 源极侧导电材料部分和漏极侧导电材料部分邻接至少一个介电材料层的两个部分。 栅极导体位于源极侧导电材料部分和漏极侧导电材料部分之间的至少一个介电材料层上。 半导体岛的电位响应于栅极导体处的电压，以使得能够或不使穿过至少一个电介质材料层的两个部分的隧穿电流。 还提供了用于半导体器件的设计结构。

公开(公告)号：US08338863B2

公开(公告)日：2012-12-25

申请号：US13467385

申请日：2012-05-09

申请人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Qizhi Liu

发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Qizhi Liu

IPC分类号： H01L29/737

CPC分类号： H01L29/7375 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/66242

摘要： Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

摘要翻译： 具有降低的基极 - 集电极结电容的垂直异质结双极晶体管，以及用于BiCMOS集成电路的垂直异质结双极晶体管和设计结构的制造方法。 垂直异质结双极晶体管包括在本征基极和外部基极之间的阻挡层或阻挡掺杂剂从外部基极扩散到本征基极的阻挡层。 阻挡层具有至少一个开口，其允许本征基底与设置在开口中的非本征基底的一部分之间直接接触。

公开(公告)号：US20120221987A1

公开(公告)日：2012-08-30

申请号：US13467385

申请日：2012-05-09

申请人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Qizhi Liu

发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Qizhi Liu

IPC分类号： G06F17/50

CPC分类号： H01L29/7375 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/66242

摘要： Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

摘要翻译： 具有降低的基极 - 集电极结电容的垂直异质结双极晶体管，以及用于BiCMOS集成电路的垂直异质结双极晶体管和设计结构的制造方法。 垂直异质结双极晶体管包括在本征基极和外部基极之间的阻挡层或阻挡掺杂剂从外部基极扩散到本征基极的阻挡层。 阻挡层具有至少一个开口，其允许本征基底与设置在开口中的非本征基底的一部分之间直接接触。

公开(公告)号：US20120205627A1

公开(公告)日：2012-08-16

申请号：US13456634

申请日：2012-04-26

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/775 ,  G06F17/50

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L21/76264 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

摘要翻译： 半导体电路包括多个半导体器件，每个半导体器件包括具有至少一个电掺杂剂原子并位于绝缘体层上的半导体岛。 每个半导体岛由包括至少一个介电材料部分的电介质材料包封。 导电材料部分，其至少一个邻接两个不同的半导体岛的两个电介质材料部分，直接位于至少一个电介质材料层上。 提供至少一个栅极导体，其覆盖至少两个半导体岛。 跨越半导体岛和导电材料部分之间的电介质材料部分的传导是通过量子隧穿实现的。 导电材料部分和至少一个栅极导体用于形成具有低漏电流的半导体电路。 还提供了用于半导体电路的设计结构。

公开(公告)号：US08242542B2

公开(公告)日：2012-08-14

申请号：US12644895

申请日：2009-12-22

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/76

CPC分类号： H01L29/127 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7606 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

摘要翻译： 半导体器件包括具有至少一个电掺杂剂原子并由包括至少一个电介质材料层的电介质材料包封的半导体岛。 所述至少一个电介质材料层的至少两部分具有小于2nm的厚度以实现量子隧道效应。 源极侧导电材料部分和漏极侧导电材料部分邻接至少一个介电材料层的两个部分。 栅极导体位于源极侧导电材料部分和漏极侧导电材料部分之间的至少一个介电材料层上。 半导体岛的电位响应栅极导体处的电压，以使得能够或不使穿过至少一个电介质材料层的两个部分的隧穿电流。 还提供了用于半导体器件的设计结构。

公开(公告)号：US20100213547A1

公开(公告)日：2010-08-26

申请号：US12644895

申请日：2009-12-22

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/786 ,  H01L21/336 ,  G06F17/50

CPC分类号： H01L29/127 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7606 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

摘要翻译： 半导体器件包括具有至少一个电掺杂剂原子并由包括至少一个电介质材料层的电介质材料包封的半导体岛。 所述至少一个电介质材料层的至少两部分具有小于2nm的厚度以实现量子隧道效应。 源极侧导电材料部分和漏极侧导电材料部分邻接至少一个介电材料层的两个部分。 栅极导体位于源极侧导电材料部分和漏极侧导电材料部分之间的至少一个介电材料层上。 半导体岛的电位响应栅极导体处的电压，以使得能够或不使穿过至少一个电介质材料层的两个部分的隧穿电流。 还提供了用于半导体器件的设计结构。

公开(公告)号：US07453151B2

公开(公告)日：2008-11-18

申请号：US11460314

申请日：2006-07-27

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L29/80

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。