公开(公告)号：US20110312147A1

公开(公告)日：2011-12-22

申请号：US12967268

申请日：2010-12-14

申请人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

发明人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC分类号： H01L21/331

CPC分类号： H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

摘要： Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

摘要翻译： 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定的导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

公开(公告)号：US20130146947A1

公开(公告)日：2013-06-13

申请号：US13323977

申请日：2011-12-13

申请人： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

发明人： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/737 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

摘要： A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.

摘要翻译： 公开了一种自对准双极晶体管及其制造方法。 在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。 形成第一开口，暴露外部基底的表面的一部分。 在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。 去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。 在第一和第二槽中的每一个中的暴露的本征和/或非本征基极层上选择性地生长硅层条纹，基本上填充相应的槽。

公开(公告)号：US08513084B2

公开(公告)日：2013-08-20

申请号：US12967268

申请日：2010-12-14

申请人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

发明人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC分类号： H01L21/331

CPC分类号： H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

摘要： Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

摘要翻译： 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

公开(公告)号：US08716096B2

公开(公告)日：2014-05-06

申请号：US13323977

申请日：2011-12-13

申请人： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

发明人： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/737 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

摘要： A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.

摘要翻译： 公开了一种自对准双极晶体管及其制造方法。 在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。 形成第一开口，暴露外部基底的表面的一部分。 在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。 去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。 在第一和第二槽中的每一个中的暴露的本征和/或非本征基极层上选择性地生长硅层条纹，基本上填充相应的槽。

公开(公告)号：US20110309471A1

公开(公告)日：2011-12-22

申请号：US12817249

申请日：2010-06-17

申请人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7378

摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。

公开(公告)号：US08405186B2

公开(公告)日：2013-03-26

申请号：US12817249

申请日：2010-06-17

申请人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

IPC分类号： H01L21/70

CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7378

摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。

公开(公告)号：US09053939B2

公开(公告)日：2015-06-09

申请号：US13303248

申请日：2011-11-23

申请人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

发明人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

IPC分类号： H01L29/737 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.

摘要翻译： 异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

公开(公告)号：US08921194B2

公开(公告)日：2014-12-30

申请号：US13294697

申请日：2011-11-11

申请人： David L. Harame ,  Qizhi Liu

发明人： David L. Harame ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L21/8228 ,  H01L21/8224 ,  H01L29/66 ,  H01L27/082 ,  H01L29/737 ,  H01L29/10

CPC分类号： H01L29/735 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/7371

摘要： Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.

摘要翻译： 横向PNP双极结晶体管，用于制造横向PNP双极结型晶体管的方法，以及横向PNP双极结型晶体管的设计结构。 横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。 源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。 基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。 发射极通过基座触点与收集器横向分开。 另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

公开(公告)号：US20140021587A1

公开(公告)日：2014-01-23

申请号：US13551971

申请日：2012-07-18

申请人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

发明人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/66 ,  H01L29/73

CPC分类号： H01L29/66234 ,  H01L29/0804 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/732

摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

摘要翻译： 本发明的方面提供了一种自对准发射极的双极晶体管。 在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间​​形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

公开(公告)号：US07002221B2

公开(公告)日：2006-02-21

申请号：US10604988

申请日：2003-08-29

申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

IPC分类号： H01L23/62

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.