公开(公告)号：US20100155896A1

公开(公告)日：2010-06-24

申请号：US12716692

申请日：2010-03-03

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L29/73

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US07371650B2

公开(公告)日：2008-05-13

申请号：US10532894

申请日：2003-10-24

Applicant: Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

Inventor： Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

IPC: H01L21/331

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US20060171116A1

公开(公告)日：2006-08-03

申请号：US11324789

申请日：2006-01-03

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Herbert Schafer

IPC: H05K7/20

CPC classification number: H01L23/473 ,  H01L21/30604 ,  H01L21/3063 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract translation: 提供一种集成电路装置及其制造方法。 至少一个集成电子部件布置在基板的主要区域。 该部件布置在基板中，或者通过电绝缘区域与基板隔离。 主通道形成在基板上并且沿着主区域布置。 每个主通道相对于纵向轴线横向地完全被基底包围。 横向通道相对于主通道横向布置。 每个横向通道打开至少一个主通道。 超过十个横向通道进入主通道。

公开(公告)号：US20060040456A1

公开(公告)日：2006-02-23

申请号：US11240297

申请日：2005-09-30

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area (32, 34) of a first conductivity type (p) is provided above a semiconductor substrate (1); a connecting area (40) of the first conductivity type (p ) is provided above the semiconductor area (32, 34); a first insulating area (35″) is provided above the connecting area (40); a window (F) is formed within the first insulating area (35″) and the connecting area (40) so as to at least partly expose the semiconductor area (32, 34); a sidewall spacer (80) is provided in the window (F) in order to insulate the connecting area (40); a second semiconductor area (60) of the second conductivity type (n+) is provided so as to cover the sidewall spacer (80) and a portion of the surrounding first insulating area (35″); the surrounding first insulating area (35″) and the sidewall spacer (80) are removed in order to form a gap (LS) between the connecting area (40) and the second semiconductor area (60); and the gap (LS) is sealed by means of a second insulating area (100) while a gaseous atmosphere or a vacuum atmosphere is provided inside the sealed gap (LS).

Abstract translation: 本发明涉及一种用于制造双极型半导体元件，特别是双极晶体管的方法和相应的双极半导体元件。 本发明的方法包括以下步骤：第一导电类型（p）的第一半导体区域（32,34）设置在半导体衬底（1）的上方; 在半导体区域（32,34）的上方设置第一导电类型（p +）的连接区域（40）。 第一绝缘区域（35“）设置在连接区域40上方; 在第一绝缘区域（35“）和连接区域（40）内形成窗口（F），以便至少部分地暴露半导体区域（32,34）; 在窗口（F）中设置侧壁间隔件（80）以使连接区域（40）绝缘; 提供第二导电类型（n +）的第二半导体区域（60），以覆盖侧壁间隔物（80）和周围的第一绝缘区域（35“）的一部分; 为了在连接区域（40）和第二半导体区域（60）之间形成间隙（LS），除去周围的第一绝缘区域（35“）和侧壁间隔物（80） 并且在所述密封间隙（LS）的内部设置有气氛或真空气氛的同时，所述间隙（LS）借助于第二绝缘区域（100）密封。

公开(公告)号：US20060009002A1

公开(公告)日：2006-01-12

申请号：US10532894

申请日：2003-10-24

Applicant: Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

Inventor： Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

IPC: H01L21/331 ,  H01L21/8228

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US06469887B2

公开(公告)日：2002-10-22

申请号：US10011133

申请日：2001-11-13

Applicant: Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

Inventor： Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

IPC: H01G406

CPC classification number: H01L27/1085 ,  H01L21/31604 ,  H01L28/40 ,  H01L28/56

Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

公开(公告)号：US5945704A

公开(公告)日：1999-08-31

申请号：US105945

申请日：1998-06-26

Applicant: Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

Inventor： Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119 ,  H01L27/76

CPC classification number: H01L27/10861 ,  H01L29/945

Abstract: A trench capacitor with an epi layer in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

Abstract translation: 具有沟槽下部的外延层的沟槽式电容器。 外延层用作沟槽电容器的掩埋板。 扩散区域围绕沟槽的下部以增强外延层的掺杂剂浓度。 扩散区域通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。

公开(公告)号：US5326718A

公开(公告)日：1994-07-05

申请号：US950068

申请日：1992-09-23

Applicant: Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

Inventor： Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor.

Abstract translation: 一种用于制造适合用作晶体管的有源部分的横向受限的单晶区域的方法。