公开(公告)号：US08476672B2

公开(公告)日：2013-07-02

申请号：US13201370

申请日：2011-04-02

申请人： Ru Huang ,  Lijie Zhang

发明人： Ru Huang ,  Lijie Zhang

IPC分类号： H01L29/86 ,  H01L21/329

CPC分类号： H01L29/87 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.

摘要翻译： 本发明提供一种ESD保护装置，其包括SCR结构，其是分别通过在硅衬底上的N阱和P阱中执行P型注入和N型注入而形成的横向PNPN结构，其中 N阱中的P型掺杂区域用作阳极，P阱中的N型掺杂区域用作阴极，其特征在于，将N型掺杂剂注入到N阱中， 形成电阻器的一个引出端子，将P型掺杂剂注入到P阱中以形成用于电阻器的另一引出端子，并且两个引出端子由电阻器连接。

公开(公告)号：US20130141183A1

公开(公告)日：2013-06-06

申请号：US13641647

申请日：2012-04-16

申请人： Le Ye ,  Jiayi Wang ,  Huailin Liao ,  Ru Huang

发明人： Le Ye ,  Jiayi Wang ,  Huailin Liao ,  Ru Huang

IPC分类号： H01P5/16

CPC分类号： H01P5/184 ,  H01P5/187

摘要： A directional coupler is disclosed integrated on a single chip and an integrated circuit based on a standard CMOS process and relates to a field of radio frequency communication. In exemplary implementations, by using a standard CMOS process technology, the directional coupler integrated by a CMOS process is formed by a coil winded by a upper layer of metal lines, a coil winded by a lower layer of metal lines, two tuning capacitor array, and a matching resistor. Two terminals of the coil are a direct terminal and an input terminal; two terminals of the coil are a coupled terminal and an isolation terminal; the terminals of the coils and are intersected at 90°; the coil is winded by an upper metal layer and the coil is winded by a lower metal layer. Further, the insertion loss is low and the isolation degree is large.

摘要翻译： 公开了一种集成在单个芯片上的定向耦合器和基于标准CMOS工艺的集成电路，涉及射频通信领域。 在示例性实施方案中，通过使用标准CMOS工艺技术，由CMOS工艺集成的定向耦合器由金属线上层缠绕的线圈，由金属线下层缠绕的线圈，两个调谐电容器阵列， 和匹配电阻。 线圈的两个端子是直接端子和输入端子; 线圈的两个端子是耦合端子和隔离端子; 线圈的端子和90°相交; 线圈被上金属层缠绕，线圈被下金属层缠绕。 此外，插入损耗低，隔离度大。

公开(公告)号：US20130069126A1

公开(公告)日：2013-03-21

申请号：US13519857

申请日：2012-02-21

申请人： Ru Huang ,  Zhiqiang Li ,  Xia An ,  Yue Guo ,  Xing Zhang

发明人： Ru Huang ,  Zhiqiang Li ,  Xia An ,  Yue Guo ,  Xing Zhang

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L29/41783 ,  H01L29/0895 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/78

摘要： An embodiment of the invention provides a germanium-based NMOS device and a method for fabricating the same, which relates to fabrication process technology of an ultra-large-scale-integrated (ULSI) circuit. The germanium-based NMOS device has two dielectric layer interposed between a metal source/drain and a substrate. The bottom dielectric layer includes a dielectric material having a high pinning coefficient S such as hafnium oxide, silicon nitride, hafnium silicon oxide or the like, and the top dielectric layer includes a dielectric material having a low conduction band offset ΔEC such as titanium oxide, gallium oxide, strontium titanium oxide or the like. According to the method, Fermi level pinning effect can be alleviated, electron barrier height can be lowered, and thus performance of the germanium-based Schottky NMOS device can be improved. Compared with a conventional single dielectric layer such as aluminum oxide (Al2O3), Schottky barrier height can be lowered while low source/drain resistances can be maintained, and thus performance of the device can be significantly improved.

摘要翻译： 本发明的实施例提供了一种基于锗的NMOS器件及其制造方法，涉及超大规模集成（ULSI）电路的制造工艺技术。 锗基NMOS器件具有介于金属源极/漏极和衬底之间的两个介电层。 底部电介质层包括具有高钉扎系数S的介电材料，例如氧化铪，氮化硅，氧化铪等，并且顶部电介质层包括具有低导带偏移＆Dgr; EC的介电材料，例如钛 氧化物，氧化镓，氧化钛锶等。 根据该方法，可以减轻费米能级钉扎效应，降低电子势垒高度，从而提高锗基肖特基NMOS器件的性能。 与常规的单一电介质层如氧化铝（Al2O3）相比，可以降低肖特基势垒高度，同时保持低的源极/漏极电阻，从而显着提高器件的性能。

公开(公告)号：US20130013245A1

公开(公告)日：2013-01-10

申请号：US13499275

申请日：2011-10-28

申请人： Ru Huang ,  Dong Yang ,  Fei Tan ,  Xia An ,  Xing Zhang

发明人： Ru Huang ,  Dong Yang ,  Fei Tan ,  Xia An ,  Xing Zhang

IPC分类号： G01R31/26 ,  G06F19/00

CPC分类号： G01R31/2621 ,  H01L22/14

摘要： The present invention discloses a method for obtaining a distribution of charges along a channel of a MOS transistor, which is used for obtaining distributions of interface states charges and charges of a gate dielectric layer in the MOS transistor. The method includes: adding a MOS transistor into a test circuit; measuring two charge pumping current curves when a source terminal is open-circuited or when a drain terminal is open-circuited before and after a stress is applied by using a charge pumping current test method, where one of the two charge pumping current curves is an original curve and the other one is an post-stress curve; finding a point B corresponding to a point A on the original curve on the post-stress curve, and estimating amount of locally-generated interface states charges and charges of the gate dielectric layer by a variation of the charge pumping current and a variation in a voltage at a local point. As compared with a conventional method for obtaining a distribution, the method of the present invention can obtain a distribution of charges along a direction form the drain or source terminal to the channel more easily and rapidly, with an aid of a computer. A mass of complicated and repeated tests are reduced. Also, the method can provide an effective base for improving device reliability.

摘要翻译： 本发明公开了一种用于获得沿着MOS晶体管的沟道的电荷分布的方法，用于获得MOS晶体管中的界面态电荷和栅介质层的电荷的分布。 该方法包括：将MOS晶体管添加到测试电路中; 当源极端子开路时，或者在通过使用电荷泵浦电流测试方法施加应力之前和之后漏极端子开路时，测量两个电荷泵浦电流曲线，其中两个电荷泵浦电流曲线之一为 原曲线，另一个是后应力曲线; 找到对应于后应力曲线上的原始曲线上的点A的点B，并且通过电荷泵浦电流的变化和局部产生的界面的变化来估计局部产生的界面状态的电介质层的电荷和电荷 电压在本地点。 与用于获得分布的常规方法相比，本发明的方法可以借助于计算机，更容易和快速地获得沿着从漏极或源极端子到达通道的方向的电荷分布。 大量复杂和重复的测试减少了。 此外，该方法可以提供用于提高装置可靠性的有效基础。

公开(公告)号：US20120181584A1

公开(公告)日：2012-07-19

申请号：US13318329

申请日：2011-04-01

申请人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Yangyuan Wang

发明人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Yangyuan Wang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/435

摘要： The invention discloses a resistive field effect transistor (ReFET) having an ultra-steep subthreshold slope, which relates to a field of field-effect-transistor logic device and circuit in CMOS ultra-large-scale-integrated circuit (ULSI). The resistive field effect transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a doped source region and a doped drain region, wherein the control gate is configured to adopt a stacked gate structure in which a bottom layer or a bottom electrode layer, a middle layer or a resistive material layer, and a top layer or a top electrode layer are sequentially formed. Compared with the existing methods for breaking the conventional subthreshold slope limititation, the device of the invention has a larger on-current, a lower operation voltage, and a better subthreshold feature.

摘要翻译： 本发明公开了一种具有超陡亚阈值斜率的电阻场效应晶体管（ReFET），其涉及CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件和电路的场。 电阻场效应晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，掺杂源极区域和掺杂漏极区域，其中控制栅极被配置为采用堆叠栅极结构，其中底层或 顺序地形成底部电极层，中间层或电阻材料层，顶层或顶部电极层。 与现有的破坏常规阈值斜率限制的方法相比，本发明的器件具有较大的导通电流，较低的工作电压和更好的亚阈值特性。

公开(公告)号：US20120168770A1

公开(公告)日：2012-07-05

申请号：US13391270

申请日：2011-11-18

申请人： Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

发明人： Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

IPC分类号： H01L29/20 ,  H01L29/12

CPC分类号： H01L23/38 ,  H01L23/3738 ,  H01L2924/0002 ,  H01L2924/00

摘要： A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.

摘要翻译： 提供了微电子领域的芯片的散热结构。 散热结构包括通过氧化隔离在芯片的上表面上形成的P型超晶格层和N型超晶格层。 P型超晶格和N型超晶格被氧化硅隔离。 通过接触孔，P型超晶格与在芯片中施加低电位的金属层电连接，并且在P型超晶格上形成与外部电源连接的金属层。 通过接触孔，N型超晶格电连接到在芯片中施加高电位电源的金属层，并且在N型超晶格上形成与外部电源连接的金属层 。 与P型超晶格连接的外部电源的电位低于与N型超晶格连接的外部电源的电位。 本发明可以实现芯片的散热，同时通过使用超晶格具有低导热性和声子定位的特性的特征，同时防止环境热量转移到芯片中。

公开(公告)号：US20120018775A1

公开(公告)日：2012-01-26

申请号：US13201370

申请日：2011-04-02

申请人： Ru Huang ,  Lijie Zhang

发明人： Ru Huang ,  Lijie Zhang

IPC分类号： H01L29/86 ,  H01L21/329

CPC分类号： H01L29/87 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.

摘要翻译： 本发明提供一种ESD保护装置，其包括SCR结构，其是分别通过在硅衬底上的N阱和P阱中执行P型注入和N型注入而形成的横向PNPN结构，其中 N阱中的P型掺杂区域用作阳极，P阱中的N型掺杂区域用作阴极，其特征在于，将N型掺杂剂注入到N阱中， 形成电阻器的一个引出端子，将P型掺杂剂注入到P阱中以形成用于电阻器的另一引出端子，并且两个引出端子由电阻器连接。

公开(公告)号：US09147597B2

公开(公告)日：2015-09-29

申请号：US14344050

申请日：2012-06-14

申请人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

发明人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76232 ,  H01L21/02052 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/28255 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/763

摘要： Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

摘要翻译： 本文公开了一种用于隔离锗基MOS器件中的有源区的方法。 基于锗的衬底的表面被薄的多晶硅层或多晶硅层覆盖，并且通过两个步骤形成由二氧化硅层或顶部的SiGe氧化物层覆盖的二氧化锗的隔离结构 在活性区域的情况下的氧化被保护。 使用多晶硅层或多晶硅层作为牺牲层的这两个氧化步骤有利于提高制造的二氧化锗的隔离质量，并且减少在局部场氧氧化期间发生的喙效应，从而显着提升 锗器件的性能。

公开(公告)号：US09086448B2

公开(公告)日：2015-07-21

申请号：US13504433

申请日：2011-11-30

申请人： Ru Huang ,  Dong Yang ,  Xia An ,  Xing Zhang

发明人： Ru Huang ,  Dong Yang ,  Xia An ,  Xing Zhang

IPC分类号： G01R31/26 ,  G06F19/00 ,  G01R31/28

CPC分类号： G01R31/287

摘要： A method for predicting a reliable lifetime of a SOI MOSFET device including: measuring a relationship of a gate resistance of the device varying as a function of a temperature at different wafer temperatures; performing a lifetime accelerating test on the device at different wafer temperatures, so as to obtain a degenerating relationship of a parameter representing the lifetime of the device as a function of stress time, and obtain a lifetime in the presence of self-heating when the parameter degenerates to 10%; performing a self-heating correction on the measured lifetime of the device by using the measured self-heating temperature and an Arrhenius model, so as to obtain a lifetime without self-heating influence; performing a self-heating correction on a variation of the drain current caused by self-heating; performing a self-heating correction on an impact ionization rate caused by hot carriers; and predicting the lifetime of the device under a bias.

摘要翻译： 一种用于预测SOI MOSFET器件的可靠寿命的方法，包括：测量在不同晶片温度下作为温度变化的器件的栅极电阻的关系; 在不同的晶片温度下在器件上进行寿命加速测试，以获得表示器件寿命的参数作为应力时间的函数的退化关系，并且当参数为自加热时，在自加热的情况下获得寿命 退化为10％; 通过使用测量的自热温度和Arrhenius模型对器件的测量寿命进行自加热校正，以获得没有自热影响的寿命; 对由自加热引起的漏极电流的变化进行自热校正; 对热载体产生的冲击电离率进行自热校正; 并预测设备的使用寿命。

公开(公告)号：US20150031188A1

公开(公告)日：2015-01-29

申请号：US14344050

申请日：2012-06-14

申请人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

发明人： Ming Li ,  Min Li ,  Ru Huang ,  Xia An ,  Xing Zhang

IPC分类号： H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/02052 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/28255 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/763

摘要： Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

摘要翻译： 本文公开了一种用于隔离锗基MOS器件中的有源区的方法。 基于锗的衬底的表面被薄的多晶硅层或多晶硅层覆盖，并且通过两个步骤形成由二氧化硅层或顶部的SiGe氧化物层覆盖的二氧化锗的隔离结构 在活性区域的情况下的氧化被保护。 使用多晶硅层或多晶硅层作为牺牲层的这两个氧化步骤有利于提高制造的二氧化锗的隔离质量，并且减少在局部场氧氧化期间发生的喙效应，从而显着提升 锗器件的性能。