公开(公告)号：US20190318775A1

公开(公告)日：2019-10-17

申请号：US16142954

申请日：2018-09-26

Applicant: Samsung Electronics Co., LTD.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl

IPC: G11C11/22

Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

公开(公告)号：US20190280694A1

公开(公告)日：2019-09-12

申请号：US16137227

申请日：2018-09-20

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Titash Rakshit

IPC: H03K19/0944 ,  H01L29/51 ,  H01L27/118 ,  H03K19/20 ,  G06N3/063

Abstract: A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.

公开(公告)号：US20190080230A1

公开(公告)日：2019-03-14

申请号：US15849106

申请日：2017-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G06N3/063 ,  G06F7/544

Abstract: A hardware device and method for performing a multiply-accumulate operation are described. The device includes inputs lines, weight cells and output lines. The input lines receive input signals, each of which is has a magnitude and a phase and can represent a complex value. The weight cells couple the input lines with the output lines. Each of the weight cells has an electrical admittance corresponding to a weight. The electrical admittance is programmable and capable of being complex valued. The input lines, the weight cells and the output lines form a crossbar array. Each of the output lines provides an output signal. The output signal for an output line is a sum of an input signal for each of the input lines connected to the output line multiplied by the electrical admittance of each of the weight cells connecting the input lines to the output line.

公开(公告)号：US10205025B2

公开(公告)日：2019-02-12

申请号：US15276779

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

公开(公告)号：US20190026627A1

公开(公告)日：2019-01-24

申请号：US15891220

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G06N3/063 ,  G06N3/04

Abstract: A neuromorphic architecture for providing variable precision in a neural network, through programming. Logical pre-synaptic neurons are formed as configurable sets of physical pre-synaptic artificial neurons, logical post-synaptic neurons are formed as configurable sets of physical post-synaptic artificial neurons, and the logical pre-synaptic neurons are connected to the logical post-synaptic neurons by logical synapses each including a set of physical artificial synapses. The precision of the weights of the logical synapses may be varied by varying the number of physical pre-synaptic artificial neurons in each of the logical pre-synaptic neurons, and/or by varying the number of physical post-synaptic artificial neurons in each of the logical post-synaptic neurons.

公开(公告)号：US20190012593A1

公开(公告)日：2019-01-10

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/423

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US09698234B2

公开(公告)日：2017-07-04

申请号：US14666770

申请日：2015-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Mark S. Rodder ,  Wei-E Wang

IPC: H01L21/31 ,  H01L31/113 ,  H01L29/51 ,  H01L21/28 ,  H01L29/778

CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/778

Abstract: Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment to form a new interface layer that incorporates material from the substrate and material from the first dielectric layer; and performing gate stack processing, including deposition of a gate electrode.

公开(公告)号：US09601586B1

公开(公告)日：2017-03-21

申请号：US15017352

申请日：2016-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Mark S. Rodder

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a metal layer on source/drain regions of respective semiconductor structures, after replacing a dummy gate structure of the semiconductor device with a metal gate structure. The method includes forming a contact structure that overlaps the metal layer on one or more, but not all, of the semiconductor structures. Moreover, an insulating material is between the source/drain regions.

公开(公告)号：US09484423B2

公开(公告)日：2016-11-01

申请号：US14270690

申请日：2014-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Jorge A. Kittl ,  Mark. S. Rodder

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/78681 ,  H01L29/78696

Abstract: A field effect transistor includes a body layer comprising a crystalline semiconductor channel region therein, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer, and a crystalline semiconductor gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Abstract translation: 场效应晶体管包括其中包括晶体半导体沟道区的主体层，以及沟道区上的栅叠层。 栅极堆叠包括晶体半导体栅极层和栅极层和沟道区之间的晶体半导体栅极介电层。 还讨论了相关设备和制造方法。

公开(公告)号：US09431529B2

公开(公告)日：2016-08-30

申请号：US14625376

申请日：2015-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Robert C. Bowen

IPC: H01L29/745 ,  H01L29/74 ,  H01L29/768 ,  H01L27/095 ,  H01L21/335 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

Abstract: Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal.

Abstract translation: 公开了用于半金属晶体管的示例性实施例，包括：与金属接触相邻的半金属接触区域; 至少一个半导体端子; 以及连接在所述接触区域和所述半导体端子之间的半金属过渡区域，所述半金属过渡区域从从所述接触区域的界面开始的半金属基本上为零的间隙向具有朝向所述半导体端子的能带隙的半导体转变。