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    Two-dimensional array-based neuromorphic processor and implementing method
    63.
    发明授权
    Two-dimensional array-based neuromorphic processor and implementing method 有权

    公开(公告)号：US11663451B2

    公开(公告)日：2023-05-30

    申请号：US16274547

    申请日：2019-02-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungho Kim ,  Cheheung Kim ,  Jaeho Lee

    IPC: G06N3/063 ,  G06F7/523 ,  G06F7/50

    CPC classification number: G06N3/063 ,  G06F7/50 ,  G06F7/523 ,  G06F2207/4824

    Abstract: A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform a multi-bit operation by using the operation values and the time information.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    65.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11450396B2

    公开(公告)日：2022-09-20

    申请号：US17398434

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

    IPC: G11C29/18 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12

    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    66.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220020445A1

    公开(公告)日：2022-01-20

    申请号：US17398434

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

    IPC: G11C29/18 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44

    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    68.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210012849A1

    公开(公告)日：2021-01-14

    申请号：US16795730

    申请日：2020-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

    IPC: G11C29/18 ,  G11C29/00 ,  G11C29/44 ,  G11C29/42

    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

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