公开(公告)号：US20210193207A1

公开(公告)日：2021-06-24

申请号：US16876553

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: G11C11/22 ,  H01L29/51 ,  H01L29/78

Abstract: A nonvolatile memory cell resistance change type nonvolatile memory cell configured to store information by changing an electrical resistance according to application of electrical stress is provided and a nonvolatile memory device including the nonvolatile memory cell is provided. The resistance change type nonvolatile memory cell includes a resistance change material layer including a resistance change material; a ferroelectric layer on a first side of the resistance change material layer, the ferroelectric layer configured to change an electrical resistance of the resistance change material layer according to a polarization direction and polarization size of a ferroelectric therein; a first electrode on the ferroelectric layer and configured to control the polarization direction and the polarization size of the ferroelectric based on an applied voltage; and a second electrode and a third electrode on the resistance change material layer with the first electrode therebetween.

公开(公告)号：US20210035635A1

公开(公告)日：2021-02-04

申请号：US16802803

申请日：2020-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Jungho YOON ,  Cheolseong HWANG ,  Soichiro MIZUSAKI ,  Youngjin CHO

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

公开(公告)号：US20170308328A1

公开(公告)日：2017-10-26

申请号：US15492436

申请日：2017-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Young LIM ,  Ki-Seok OH ,  Sungyong SEO ,  Youngjin CHO ,  Insu CHOI

IPC: G06F3/06 ,  G11C11/406

Abstract: A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.

公开(公告)号：US20170235524A1

公开(公告)日：2017-08-17

申请号：US15421514

申请日：2017-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkwang YOO ,  Youngjin CHO ,  Han-Ju LEE ,  JinHyeok CHOI

IPC: G06F3/06 ,  G06F12/0868

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/202 ,  G11C8/12 ,  G11C2207/2245

Abstract: A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

公开(公告)号：US20170188456A1

公开(公告)日：2017-06-29

申请号：US15133352

申请日：2016-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Hyeon Cheol PARK ,  Kwanghee KIM ,  Weonho SHIN ,  Daejin YANG

IPC: H05K1/09 ,  H01L51/52 ,  G06F3/047 ,  H05K1/02

CPC classification number: H05K1/09 ,  G06F3/041 ,  G06F3/047 ,  G06F2203/04102 ,  H01B1/02 ,  H01B1/023 ,  H01B1/026 ,  H01B1/16 ,  H01L51/5206 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/5338 ,  H05K1/0274 ,  H05K2201/0108 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2201/0373 ,  H05K2201/0379 ,  H05K2201/0391 ,  H05K2201/09681 ,  H05K2201/10128

Abstract: A conductive component including: a substrate, a first layer comprising a plurality of island structures disposed on the substrate, wherein the island structures include graphene; and a second layer disposed on the first layer, wherein the second layer includes a plurality of conductive nanowires. Also, an electronic device including the conductive component.

公开(公告)号：US20130227347A1

公开(公告)日：2013-08-29

申请号：US13716752

申请日：2012-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Hyunsik KIM

IPC: G06F13/28 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1068 ,  G06F13/28 ,  G06F2206/1014 ,  G06F2212/403

Abstract: A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device.

公开(公告)号：US20130223628A1

公开(公告)日：2013-08-29

申请号：US13674174

申请日：2012-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Hyunsik KIM

IPC: H04L9/08

CPC classification number: G06F21/78 ,  G06F12/1408 ,  G06F21/72 ,  H04L9/08 ,  H04L9/0861 ,  H04L9/0897

Abstract: A memory controller controlling a nonvolatile memory is provided. The memory controller includes an encryption key feeder configured to feed a cipher key according to a logical address transferred from a host; and an encryption engine configured to perform an encryption operation on data transferred from the host or a decryption operation on data transferred from the nonvolatile memory device, using the cipher key provided from the encryption key feeder.