公开(公告)号：US07079421B2

公开(公告)日：2006-07-18

申请号：US10848313

申请日：2004-05-19

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C11/34

CPC分类号： G11C16/102

摘要： This invention is a method of improving a data retention ability of a semiconductor memory device having a plurality of nonvolatile memory cells storing a plurality of memory states. The method includes the steps of: (a) selecting the nonvolatile memory cells in a first memory group each of which accumulates charges higher in level than a first threshold from the plurality of nonvolatile memory cells; (b) extracting the nonvolatile memory cells in a first sub-group each of which accumulates the charges lower in level than a second threshold from the nonvolatile memory cells in the first memory group; and (c) programming the nonvolatile memory cells in the first sub-group until each of the nonvolatile memory cells accumulates the charges higher in level than the second threshold.

摘要翻译： 本发明是提高具有存储多个存储器状态的多个非易失性存储单元的半导体存储器件的数据保持能力的方法。 该方法包括以下步骤：（a）选择第一存储器组中的非易失性存储单元，每个非易失性存储单元从多个非易失性存储器单元中累积比第一阈值高的电荷; （b）从第一存储器组中的非易失性存储单元中提取第一子组中的非易失性存储单元，每个非易失性存储单元累积低于第二阈值的电荷的电荷; 以及（c）对第一子组中的非易失性存储单元进行编程，直到每个非易失性存储单元累积高于第二阈值的电荷。

公开(公告)号：US20060131642A1

公开(公告)日：2006-06-22

申请号：US10530519

申请日：2003-10-01

申请人： Hiroshi Iwata ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： In a semiconductor storage device, a gate insulating film (12) and a gate electrode (13) are laid on a first conductivity type semiconductor substrate (11), and charge holding portions (10A, 10B) are formed on both sides of the gate electrode (13). Second conductivity type first and second diffusion layer regions (17, 18) are formed in regions of the semiconductor substrate (11) corresponding to the charge holding portions (10A, 10B). The charge holding portions (10A, 10B) are each structured so as to change, in accordance with an electric charge amount held in the charge holding portions, a current amount flowing from one of the second conductivity type diffusion layer regions (17, 18) to the other of the diffusion layer regions through a channel region when voltage is applied to the gate electrode (13). Part of each charge holding portion (10A, 10B) is present below an interface of the gate insulating film (12) and the channel region.

摘要翻译： 在半导体存储装置中，栅极绝缘膜（12）和栅电极（13）被放置在第一导电型半导体基板（11）上，电荷保持部（10A，10B）形成在 栅电极（13）。 第二导电类型的第一和第二扩散层区域（17,18）形成在对应于电荷保持部分（10A，10B）的半导体衬底（11）的区域中。 电荷保持部（10A，10B）分别被构造成根据保持在电荷保持部中的电荷量来改变从第二导电型扩散层区域（17， 18），当电压施加到栅电极（13）时，通过沟道区域到另一个扩散层区域。 每个电荷保持部分（10A，10B）的一部分存在于栅极绝缘膜（12）和沟道区域的界面之下。

公开(公告)号：US07061808B2

公开(公告)日：2006-06-13

申请号：US10847627

申请日：2004-05-18

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/04

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/3454 ,  G11C16/3459 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device includes a memory array; a storage section that receives a maximum pulse value from a user of the semiconductor memory device; a control section that executes a writing processing or an erasing processing for the memory array and restarts the writing or erasing processing in the case where the processing for the memory array has failed; a counter section that counts up a number of processings performed by the control section; and a detection section that detects when the number of processings is equal to the maximum pulse value to prevent the control section from restarting the writing or erasing processing.

摘要翻译： 半导体存储器件包括存储器阵列; 存储部，其从半导体存储器件的用户接收最大脉冲值; 在存储器阵列的处理失败的情况下执行对存储器阵列的写入处理或擦除处理并重新开始写入或擦除处理的控制部分; 对由所述控制部执行的处理次数进行计数的计数部; 以及检测部，其检测处理次数等于最大脉冲值，以防止控制部重新开始写入或擦除处理。

公开(公告)号：US07053437B2

公开(公告)日：2006-05-30

申请号：US10848214

申请日：2004-05-19

申请人： Hiroshi Iwata ,  Takayuki Ogura ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Takayuki Ogura ,  Akihide Shibata

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： A semiconductor memory device including memory cells, each memory cell including: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a channel region located below the gate electrode; a pair of source and drain regions arranged on a opposite sides, respectively, of the channel region, the source and drain regions having a conductive type opposite to that of the channel region; and memory functional units located on opposite sides, respectively, of the gate electrode, each memory functional unit including a charge retaining portion and an anti-dissipation insulator, the charge retaining portion being made of a material serving to store charges, the anti-dissipation insulator serving to prevent the stored charges from being dissipated by separating the charge retaining portion from both the gate electrode and the substrate, wherein a distance between a side wall of the gate electrode and a side of the charge retaining portion facing each other (T2) is adapted to differ from a distance between a bottom of the charge retaining portion and a surface of the substrate (T1).

摘要翻译： 一种包括存储单元的半导体存储器件，每个存储单元包括：形成在半导体衬底上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 位于栅电极下方的沟道区; 一对源极和漏极区分别布置在沟道区的相对侧上，源极和漏极区具有与沟道区相反的导电类型; 以及分别位于栅电极的相对侧的存储功能单元，每个存储功能单元包括电荷保持部分和消耗绝缘体，电荷保持部分由用于存储电荷的材料制成，抗耗散 绝缘体，用于通过将电荷保持部分与栅极电极和衬底分离来防止存储的电荷消散，其中栅电极的侧壁和电荷保持部分的面彼此相对的距离（T 2 ）适于不同于电荷保持部分的底部和基板（T 1）的表面之间的距离。

公开(公告)号：US20060109729A1

公开(公告)日：2006-05-25

申请号：US10528997

申请日：2003-09-10

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Kei Tokui

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Kei Tokui

IPC分类号： G11C5/14

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a first switch SW1 and turns off second and third switches SW2 and SW3, thereby supplying the input voltage to a memory cell array 21 via the first switch SW1. When the input voltage determining circuit 24 determines that the input voltage is not higher than the prescribed voltage, the control circuit 25 turns off the first switch SW1 and turns on the second and third switches SW2 and SW3, thereby supplying a voltage from a charge pump 23 via the second and third switches SW2 and SW3. By this operation, the memory element is able to retain storage of two bits or more even if miniaturized, to execute stable operation with a small circuit area and to prevent circuit malfunction attributed to a small current supplied to the memory cell array.

摘要翻译： 当输入电压确定电路24确定输入电压超过规定电压时，正极性功率选择电路22的控制电路25接通第一开关SW 1并关断第二和第三开关SW 2和SW 3，由此 通过第一开关SW 1将输入电压提供给存储单元阵列21。 当输入电压确定电路24确定输入电压不高于规定电压时，控制电路25关断第一开关SW 1并接通第二和第三开关SW 2和SW 3，从而提供来自 经由第二和第三开关SW 2和SW 3的电荷泵23。 通过该操作，即使小型化，存储元件也能够保持两位以上的存储，能够以较小的电路面积进行稳定的动作，并且防止归因于提供给存储单元阵列的小电流引起的电路故障。

公开(公告)号：US07009892B2

公开(公告)日：2006-03-07

申请号：US10850896

申请日：2004-05-20

申请人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C7/00

CPC分类号： H01L29/66833 ,  G11C7/22 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a control logic circuit for generating read selection signals each selecting one plane for reading and write selection signals each selecting one plane for writing from a plurality of planes in which memory cells are arranged in an array, an address selection circuit disposed for each of the planes, and an address buffer circuit for simultaneously providing a write address and a read address. Each of the address selection circuits is configured so as to be able to receive one of the read selection signals and one of the write selection signals from the control logic circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 一种半导体存储器件，包括用于产生读取选择信号的控制逻辑电路，每个读取选择信号选择一个平面用于读取和写入选择信号，每个选择信号从阵列中排列存储器单元的多个平面中选择一个写入平面，地址选择电路设置 以及用于同时提供写入地址和读取地址的地址缓冲器电路。 每个地址选择电路被配置为能够从控制逻辑电路接收读取选择信号中的一个和写入选择信号中的一个。 存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧并具有与沟道区域相反的导电类型的扩散区域， 以及形成在栅电极的两侧并具有保持电荷的功能的存储功能单元。

公开(公告)号：US06992926B2

公开(公告)日：2006-01-31

申请号：US10848605

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/06

CPC分类号： H01L21/28282 ,  G11C16/08 ,  H01L29/792

摘要： A semiconductor storage device is provided with a gate electrode, a semiconductor layer, a gate insulating film sandwiched between the gate electrode and the semiconductor layer, a channel region under the gate electrode, diffusion regions provided respectively on two sides of the channel regions and being of the other conductivity region than the channel region, memory elements 1 provided respectively on two sides of the gate electrode and having a function of holding charges, and a word line driver circuit, in which the CMOS technique is used. The driver circuit includes a common node for supplying a potential for activating an output inverter for driving a row word line. While the semiconductor storage device is in a read mode, a CMOS inverter other than the output inverter controls a signal at the common node, the CMOS inverter connected to a read input line. While the semiconductor storage device is in writing/erasing mode, a plurality of writing/erasing transistors connected in series to the node are activated in accordance with an address signal, in order to lower the common node to a low potential.

摘要翻译： 半导体存储装置设置有栅电极，半导体层，夹在栅极电极和半导体层之间的栅极绝缘膜，栅电极下方的沟道区域，分别设置在沟道区域的两侧的扩散区域， 的另一个导电区域，分别设置在栅电极的两侧并具有保持电荷的功能的存储元件1和使用CMOS技术的字线驱动电路。 驱动器电路包括用于提供用于激活用于驱动行字线的输出反相器的电位的公共节点。 当半导体存储装置处于读取模式时，除了输出反相器之外的CMOS反相器控制公共节点处的信号，CMOS反相器连接到读取输入线。 当半导体存储装置处于写入/擦除模式时，根据地址信号激活与该节点串联连接的多个写/擦除晶体管，以便将公共节点降低到低电位。

公开(公告)号：US06975551B2

公开(公告)日：2005-12-13

申请号：US10483064

申请日：2002-07-09

申请人： Hiroshi Iwata ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C11/406 ,  G11C11/407 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L29/7881 ,  G11C11/406 ,  G11C2207/2227 ,  G11C2211/4067 ,  H01L29/42332 ,  H01L29/792

摘要： While a memory section (1) is in standby mode, a power supply/interruption circuit (2) supplies electric power to a memory section (1) only during periods in which a refresh operation is performed in synchronization with a timing of the refresh operation generated by the clock circuit (3), and interrupts power supply to the memory section (1) during periods in which the refresh operation is not performed. Thus, power consumption of the memory section that performs the refresh operations is suppressed, by which a power consumption reduction of the semiconductor storage device is realized.

摘要翻译： 当存储器部分（1）处于待机模式时，电源/中断电路（2）仅在与更新操作的定时同步地进行刷新操作的时段期间向存储器部分（1）供电 由时钟电路（3）产生，并且在不执行刷新操作的时段期间中断对存储器部分（1）的供电。 因此，抑制执行刷新操作的存储部分的功耗，从而实现半导体存储装置的功耗降低。

公开(公告)号：US20050002244A1

公开(公告)日：2005-01-06

申请号：US10848481

申请日：2004-05-19

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/22 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C29/838 ,  G11C16/0475 ,  G11C16/22 ,  G11C29/785 ,  G11C29/787 ,  G11C29/789 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

摘要： A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes (i) a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, (ii) a channel region provided under the gate electrode, (iii) diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and (iv) memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit includes an addressing arrangement for a single chip memory including cells associated with a plurality of redundant lines. A decoder for selecting a redundant row is selected by an address signal, and the decoder is programmed. The redundancy circuit requires no additional package pin, and programming is executed after packaging is completed. The semiconductor storage device further includes an arrangement for permanently inactivating any further programming of the redundancy circuit, in order to prevent a user from performing inadvertent programming.

摘要翻译： 半导体存储装置包括多个存储元件和冗余电路。 每个存储元件包括（i）设置在半导体层上的栅极电极，介于栅极电极和半导体层之间的栅极绝缘膜，（ii）设置在栅电极下方的沟道区域，（iii）扩散区域 设置在通道区域的两侧，扩散区域具有与沟道区域的导电类型相反的导电类型，以及（iv）分别设置在栅极电极的两侧的存储功能部件，存储功能部件具有 保持电荷的功能。 冗余电路包括用于单个芯片存储器的寻址布置，其包括与多个冗余线相关联的单元。 通过地址信号选择用于选择冗余行的解码器，并对解码器进行编程。 冗余电路不需要额外的封装引脚，封装完成后执行编程。 半导体存储装置还包括用于永久地停用冗余电路的任何进一步编程的装置，以便防止用户执行无意的编程。

公开(公告)号：US20050002240A1

公开(公告)日：2005-01-06

申请号：US10849481

申请日：2004-05-18

申请人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C29/46 ,  G11C16/04 ,  G11C16/06 ,  G11C29/14

摘要： The present invention provides a semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 本发明提供一种半导体存储器件，包括：存储单元阵列，其中存储单元被布置; 用于接受由外部用户发出的命令的多个终端; 用于在外部用户和存储单元阵列之间进行接口的命令接口电路; 用于控制编程和擦除操作的写状态机; 以及输出电路，用于向所述多个端子输出内部信号，其中所述存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在所述栅极电极下方的沟道区域，设置在所述栅极绝缘膜两侧的扩散区域 所述沟道区域具有与沟道区的导电类型相反的导电类型，以及形成在栅电极的两侧上并具有保持电荷的功能的存储功能元件。