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133 条记录 (耗时 0.035 秒)

    Methods of fabricating a semiconductor device
    62.
    发明申请
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20090155991A1

    公开(公告)日：2009-06-18

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

    Slurry compositions and CMP methods using the same
    64.
    发明授权
    Slurry compositions and CMP methods using the same 失效
    浆料组合物和使用其的CMP方法

    公开(公告)号：US07314578B2

    公开(公告)日：2008-01-01

    申请号：US10807139

    申请日：2004-03-24

    申请人： Jaekwang Choi ,  Jaedong Lee ,  Chang-Ki Hong

    发明人： Jaekwang Choi ,  Jaedong Lee ,  Chang-Ki Hong

    IPC分类号： C09K5/00

    CPC分类号： C09G1/02 ,  C09K3/1463 ,  H01L21/3212 ,  H01L21/7684

    摘要： The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The slurry compositions include one or more non-ionic polymeric surfactants that will selectively form a passivation layer on an exposed polysilicon surface in order to suppress the polysilicon removal rate relative to silicon oxide and silicon nitride and improve the planarity of the polished substrate. Exemplary surfactants include alkyl and aryl alcohols of ethylene oxide (EO) and propylene oxide (PO) block copolymers and may be present in the slurry compositions in an amount of up to about 5 wt %, although much smaller concentrations may be effective. Other slurry additives may include viscosity modifiers, pH modifiers, dispersion agents, chelating agents, and amine or imine surfactants suitable for modifying the relative removal rates of silicon nitride and silicon oxide.

    摘要翻译： 提供适用于涉及多晶硅层的化学机械抛光（CMP）的工艺的新的浆料组合物的本发明的示例性实施方案。 浆料组合物包括一种或多种非离子聚合物表面活性剂，其将在暴露的多晶硅表面上选择性地形成钝化层，以便抑制相对于氧化硅和氮化硅的多晶硅去除速率并提高抛光的基材的平面度。 示例性的表面活性剂包括环氧乙烷（EO）和环氧丙烷（PO）嵌段共聚物的烷基和芳基醇，并且可以以高达约5重量％的量存在于浆料组合物中，尽管更小的浓度可能是有效的。 其它浆料添加剂可以包括粘度调节剂，pH调节剂，分散剂，螯合剂和适于改变氮化硅和氧化硅的相对去除速率的胺或亚胺表面活性剂。

    Method of fabricating self-aligned contact pad using chemical mechanical polishing process
    65.
    发明申请
    Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
    使用化学机械抛光工艺制造自对准接触垫的方法

    公开(公告)号：US20070072407A1

    公开(公告)日：2007-03-29

    申请号：US11525490

    申请日：2006-09-23

    申请人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    发明人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/7684 ,  H01L27/10873 ,  H01L27/10885

    摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

    摘要翻译： 一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层， 覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模 具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。 该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一 蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

    Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness
    68.
    发明授权
    Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness 有权
    制造具有包括不同厚度的两个以上部分的隧道绝缘层的非易失性存储器件的方法

    公开(公告)号：US06709920B2

    公开(公告)日：2004-03-23

    申请号：US09902243

    申请日：2001-07-10

    申请人： Jae-Phil Boo ,  Soo-Young Tak ,  Kwang-Bok Kim ,  Kyung-Hyun Kim ,  Chang-Ki Hong

    发明人： Jae-Phil Boo ,  Soo-Young Tak ,  Kwang-Bok Kim ,  Kyung-Hyun Kim ,  Chang-Ki Hong

    IPC分类号： H01L218242

    CPC分类号： H01L27/11526 ,  H01L27/11531

    摘要： A method of fabricating a non-volatile memory device, which has a tunnel insulating layer consisting of two or more portions of different thickness, cell transistors, and auxiliary transistors for applying external voltage and for interfacing with peripheral circuits is described. According to the method, the tunnel insulating layer, a conductive layer, and a first insulating layer are sequentially deposited over a semiconductor substrate. The resultant structure is selectively etched to a given depth to form trenches. A second insulating layer is deposited over the substrate including the trenches, and the second insulating layer is selectively removed so as to form element isolation regions consisting of the trenches filled with the second insulating layer. The first insulating layer is selectively removed, and the second insulating layer is selectively removed by a CMP process to expose the conductive layer. The conductive layer is used as the stopping layer during the CMP process.

    摘要翻译： 描述了制造具有由不同厚度的两个或更多个部分组成的隧道绝缘层的单元晶体管和用于施加外部电压并与外围电路接口的辅助晶体管的非易失性存储器件的制造方法。 根据该方法，隧道绝缘层，导电层和第一绝缘层依次沉积在半导体衬底上。 将所得结构选择性地蚀刻到给定的深度以形成沟槽。 在包括沟槽的衬底上沉积第二绝缘层，并且选择性地去除第二绝缘层，以便形成由填充有第二绝缘层的沟槽组成的元件隔离区域。 选择性地去除第一绝缘层，并且通过CMP工艺选择性地去除第二绝缘层以暴露导电层。 在CMP工艺期间，导电层用作停止层。

    Methods of forming trench isolation structures by etching back electrically insulating layers using etching masks
    69.
    发明授权
    Methods of forming trench isolation structures by etching back electrically insulating layers using etching masks 有权
    通过使用蚀刻掩模蚀刻电绝缘层来形成沟槽隔离结构的方法

    公开(公告)号：US06169002A

    公开(公告)日：2001-01-02

    申请号：US09216192

    申请日：1998-12-18

    申请人： Chang-Ki Hong

    发明人： Chang-Ki Hong

    IPC分类号： H01L21336

    CPC分类号： H01L21/76224

    摘要： A trench is formed in the integrated circuit substrate via a mask and filled with an electrically insulating layer. The electrically insulating layer is etched back using the mask. After etching the electrically insulating layer the mask is removed. Etching the electrically insulating layer using the mask avoids the protrusion of the electrically insulating layer from the semiconductor substrate associated with the prior art and thereby may reduce the formation of grooves in the electrically insulating layer and improve the reliability of the electrically insulating layer.

    摘要翻译： 通过掩模在集成电路基板中形成沟槽并填充有电绝缘层。 使用掩模将电绝缘层回蚀刻。 在蚀刻电绝缘层之后，去除掩模。 使用掩模蚀刻电绝缘层避免了电绝缘层与现有技术相关的半导体衬底的突起，从而可以减少电绝缘层中凹槽的形成并提高电绝缘层的可靠性。

    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same
    70.
    发明授权
    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same 失效
    形成薄铁电体层的方法和制造其的半导体器件的制造方法

    公开(公告)号：US08124526B2

    公开(公告)日：2012-02-28

    申请号：US12503440

    申请日：2009-07-15

    申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

    摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

    摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。