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公开(公告)号：US20120305886A1
公开(公告)日：2012-12-06
申请号：US13572114
申请日：2012-08-10
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源极和漏极区域。
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公开(公告)号：US20120280204A1
公开(公告)日：2012-11-08
申请号：US13550700
申请日：2012-07-17
IPC分类号： H01L29/08
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.
摘要翻译： 一种纳米线场效应晶体管（FET）器件，包括源极区域，该源极区域包括设置在第二半导体层上的第一半导体层，源区域具有平行于{110}晶面的表面和与{110}晶体平行的相对侧壁表面 平面，包括设置在第二半导体层上的第一半导体层的漏极区域，源极区域具有平行于{110}晶面的面和平行于{110}晶面的相对侧壁表面，并且纳米线通道构件悬挂 源极区和漏极区，其中纳米线通道包括第一半导体层，平行于{100}晶面的相对侧壁表面和平行于{110}晶面的相对面。
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公开(公告)号：US08143113B2
公开(公告)日：2012-03-27
申请号：US12630939
申请日：2009-12-04
IPC分类号： H01L21/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译： 一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构， 在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入， 从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘 地区。
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公开(公告)号：US20120068150A1
公开(公告)日：2012-03-22
申请号：US12884707
申请日：2010-09-17
IPC分类号： H01L29/775 , H01L21/336 , H01L29/772
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/4966 , H01L29/513 , H01L29/66439 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.
摘要翻译： 一种用于形成纳米线场效应晶体管（FET）器件的方法，包括形成绝缘体上硅（SOI）焊盘区域，第二SOI焊盘区域，第三SOI焊盘区域，将第一SOI焊盘区域连接到第一SOI焊盘区域的第一SOI部分 第二SOI焊盘区域和将第二SOI焊盘区域连接到衬底上的第三SOI焊盘区域的第二SOI部分，在第二SOI部分上形成第一硬掩模层，在半导体衬底上形成第一悬浮的纳米线，形成第一 围绕第一悬浮纳米线的一部分构造栅极结构，在第一栅极结构和第一悬置纳米线上图案化第二硬掩模层，去除第一硬掩模层，在半导体衬底上形成第二悬浮纳米线，在第二栅极结构周围形成第二栅极结构 第二悬浮纳米线的一部分，以及去除第二硬掩模层。
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公开(公告)号：US20110278543A1
公开(公告)日：2011-11-17
申请号：US12778517
申请日：2010-05-12
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L29/0669 , B82Y10/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.
摘要翻译： 提供了一种修改具有设置在绝缘体上的半导体的晶片的方法，包括以不同的初始半导体厚度建立晶片的第一和第二区域，形成经由每个第一和第二区域上的相应纳米线通道连接的半导体焊盘对，并重塑 纳米线通道进入纳米线，每个纳米线具有反映第一和第二区域中的每一个处的不同初始半导体厚度的各自不同的厚度。
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公开(公告)号：US20110133167A1
公开(公告)日：2011-06-09
申请号：US12631342
申请日：2009-12-04
IPC分类号： H01L29/66 , H01L21/336 , H01L29/786
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.
摘要翻译： 一种用于形成集成电路的方法，所述方法包括形成悬置在绝缘体衬底上的第一纳米线，所述第一纳米线附接到绝缘体上的第一绝缘体（SOI）焊盘区域和设置在所述绝缘体衬底上的第二SOI焊盘区域， 布置在绝缘体基板上的第二纳米线，其连接到设置在绝缘体基板上的第三SOI焊盘区域和第四SOI焊盘区域，以及SOI板状区域，其设置在绝缘体基板上，并且形成围绕部分的第一栅极 的第一纳米线，第二纳米线的一部分上的第二栅极和SOI板区域的一部分上的第三栅极。
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公开(公告)号：US07534675B2
公开(公告)日：2009-05-19
申请号：US11850644
申请日：2007-09-05
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： Techniques for the fabrication of field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a method of fabricating a FET is provided comprising the following steps. A substrate is provided having a silicon-on-insulator (SOI) layer. At least one nanowire is deposited over the SOI layer. A sacrificial gate is formed over the SOI layer so as to cover a portion of the nanowire that forms a channel region. An epitaxial semiconductor material is selectively grown from the SOI layer that covers the nanowire and attaches the nanowire to the SOI layer in a source region and in a drain region. The sacrificial gate is removed. An oxide is formed that divides the SOI layer into at least two electrically isolated sections, one section included in the source region and the other section included in the drain region. A gate dielectric layer is formed over the channel region. A gate is formed over the channel region separated from the nanowire by the gate dielectric layer. A metal-semiconductor alloy is formed over the source and drain regions.
摘要翻译： 提供了具有纳米线通道的场效应晶体管（FET）制造技术。 一方面，提供一种制造FET的方法，包括以下步骤。 提供了具有绝缘体上硅（SOI）层的衬底。 在SOI层上沉积至少一个纳米线。 牺牲栅极形成在SOI层上，以覆盖形成沟道区的纳米线的一部分。 从覆盖纳米线的SOI层选择性地生长外延半导体材料，并将纳米线附着在源极区域和漏极区域中的SOI层。 牺牲栅被去除。 形成氧化物，其将SOI层分成至少两个电隔离部分，一个部分包括在源极区域中，另一个部分包括在漏极区域中。 栅极电介质层形成在沟道区域上。 栅极形成在通过栅极介电层与纳米线分离的沟道区上。 在源极和漏极区域上形成金属 - 半导体合金。
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公开(公告)号：US20090057762A1
公开(公告)日：2009-03-05
申请号：US11850608
申请日：2007-09-05
IPC分类号： H01L27/12
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/20 , H01L29/22 , H01L29/42392 , H01L29/458 , H01L29/66545 , H01L29/66628 , H01L29/78696 , Y10S977/762 , Y10S977/784 , Y10S977/938
摘要： Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included in a drain region; a channel region connecting the source region and the drain region and including at least one nanowire; an epitaxial semiconductor material, grown from the SOI layer, covering the nanowire and attaching the nanowire to each section of the SOI layer; and a gate over the channel region.
摘要翻译： 提供具有纳米线通道的场效应晶体管（FET）。 一方面，提供了FET。 FET包括具有绝缘体上硅（SOI）层的衬底，其被划分成彼此电隔离的至少两个部分，一个部分包括在源极区域中，另一个部分包括在漏极区域中; 连接源极区域和漏极区域并且包括至少一个纳米线的沟道区域; 从SOI层生长的外延半导体材料，覆盖纳米线并将纳米线附接到SOI层的每个部分; 和通道区域上的门。
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公开(公告)号：US09184301B2
公开(公告)日：2015-11-10
申请号：US13600598
申请日：2012-08-31
IPC分类号： H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/423
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
摘要翻译： 集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。
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公开(公告)号：US08809131B2
公开(公告)日：2014-08-19
申请号：US13550861
申请日：2012-07-17
IPC分类号： H01L21/335
CPC分类号： H01L29/66545 , H01L29/165 , H01L29/42392 , H01L29/66795 , H01L29/785
摘要： In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided.
摘要翻译： 一方面，制造纳米线FET器件的方法包括以下步骤。 提供晶片。 在堆叠中的晶片上形成至少一个牺牲层和硅层。 翅片在堆叠中被图案化。 虚拟门形成在将用作沟道区域的鳍的部分上，并且其中保持暴露的鳍的一个或多个部分将用作源极和漏极区。 围绕虚拟栅极沉积间隙填充材料并进行平面化处理。 移除在间隙填充材料中形成凹槽的伪栅极。 硅层（其将用作纳米线通道）的部分从沟槽内的翅片释放。 替代栅极形成在围绕纳米线通道的沟槽内的沟槽中，全部配置。 还提供了纳米线FET器件。
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