公开(公告)号：US06651163B1

公开(公告)日：2003-11-18

申请号：US09521248

申请日：2000-03-08

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G06F900

CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3842 ,  G06F9/3851

摘要： A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.

摘要翻译： 提供了一种用于多线程多处理器中异常和中断处理的机制。 该机制允许在多线程多处理器计算机中处理异常和中断，同时从操作系统隐藏计算机的多处理器性质。 通常，当操作系统识别计算机的多处理器性质时，处理异常和中断时可能需要额外的开销。 由于保存和恢复处理状态所涉及的开销，处理器的性能可能会受到很大的影响。 提供了额外的电路，其允许计算机的多处理器性质从操作系统中隐藏，同时最小化正确处理所需的开销。

公开(公告)号：US06351801B1

公开(公告)日：2002-02-26

申请号：US09483493

申请日：2000-01-14

申请人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

发明人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

IPC分类号： G06F926

CPC分类号： G06F9/382 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/321 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： In a microprocessor system, a program counter circuit generates a program counter value that represents a retrieved instruction and that includes a more significant portion, a less significant portion, and a carry signal for use in determining a next program counter value. An execute program counter circuit generates an execute program counter value from the less significant program counter value and from the carry signal. The execute program counter value represents a program counter value of an executed instruction.

摘要翻译： 在微处理器系统中，程序计数器电路产生表示检索到的指令的程序计数器值，并且包括用于确定下一个程序计数器值的更重要部分，较小有效部分和进位信号。 执行程序计数器电路从较不重要的程序计数器值和进位信号产生执行程序计数器值。 执行程序计数器值表示执行指令的程序计数器值。

公开(公告)号：US06230259B1

公开(公告)日：2001-05-08

申请号：US08961681

申请日：1997-10-31

申请人： David S. Christie ,  Uwe Kranich

发明人： David S. Christie ,  Uwe Kranich

IPC分类号： G06F1500

CPC分类号： G06F9/30138 ,  G06F9/30123 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30189

摘要： A microprocessor having a standard register set and an extended register set, which is configured to save its state upon suspension of either an extended register process or a standard register processor. The microprocessor is configured to execute both standard register instruction sequences and extended register instruction sequences. A first memory is provided for storing a state of the microprocessor when a standard register instruction set sequence is suspended. The microprocessor further comprises a second memory for storing a microprocessor state upon suspension of the microprocessor executing an extended register instruction set sequence. An extended state save circuit coupled between a microprocessor core and the second memory allows the extended state of the microprocessor to be stored without modification of the operating system. As a result, the extended state of the microprocessor can be saved transparently to the operating system.

摘要翻译： 具有标准寄存器组和扩展寄存器组的微处理器，其配置为在暂停扩展寄存器处理或标准寄存器处理器时保存其状态。 微处理器被配置为执行标准寄存器指令序列和扩展寄存器指令序列。 提供第一存储器，用于当暂停标准寄存器指令集序列时存储微处理器的状态。 微处理器还包括第二存储器，用于在执行扩展寄存器指令集序列的微处理器暂停时存储微处理器状态。 耦合在微处理器核心和第二存储器之间的扩展状态保存电路允许在不修改操作系统的情况下存储微处理器的扩展状态。 结果，微处理器的扩展状态可以透明地保存到操作系统。

公开(公告)号：US06185675B2

公开(公告)日：2001-02-06

申请号：US09137579

申请日：1998-08-21

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G06F938

CPC分类号： G06F9/3804 ,  G06F9/3806 ,  G06F9/3836

摘要： A cache memory configured to access stored instructions according to basic blocks is disclosed. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. A microprocessor configured to use a basic block oriented cache may comprise a basic block cache and a basic block sequence buffer. The basic block cache may have a plurality of storage locations configured to store basic blocks. The basic block sequence buffer also has a plurality of storage locations, each configured to store a block sequence entry. The block sequence entry may comprise an address tag and one or more basic block pointers. The address tag corresponds to the fetch address of a particular basic block, and the pointers point to basic blocks that follow the particular basic block in a predicted order. A system using the microprocessor and a method for caching instructions in a block oriented manner rather than conventional power-of-two memory blocks are also disclosed.

摘要翻译： 公开了一种被配置为根据基本块访问存储的指令的高速缓冲存储器。 基本块是由分支指令产生的指令流中的自然分割。 基本块的开始是分支的目标，而结束是另一个分支指令。 配置为使用基于面向块的缓存的微处理器可以包括基本块高速缓存和基本块序列缓冲器。 基本块高速缓存可以具有被配置为存储基本块的多个存储位置。 基本块序列缓冲器还具有多个存储位置，每个存储位置被配置为存储块序列条目。 块序列条目可以包括地址标签和一个或多个基本块指针。 地址标签对应于特定基本块的获取地址，并且指针指向按预测顺序跟随特定基本块的基本块。 还公开了一种使用微处理器的系统和用于以面向块方式缓存指令的方法，而不是传统的二次电力二存储块。

公开(公告)号：US6055650A

公开(公告)日：2000-04-25

申请号：US56005

申请日：1998-04-06

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F9/38 ,  G06F11/30

CPC分类号： G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A phase change monitor monitors one or more processor resources to detect a phase change in the program being executed. The phase change monitor signals a prefetch unit to indicate the detected phase change, and may also provide information regarding the phase being entered (as detected by the phase change monitor). The prefetch unit is configured to selectively prefetch in response to the detected phase changes. Prefetching may be tailored to the detected phases. The prefetch unit may disable a current prefetch generated during a previous phase upon detection of the phase change, and a new prefetch may be initiated for the phase being entered. Since the phase being entered may operate upon different data sets, the current prefetch may be less likely to be prefetching data which is subsequently accessed. Terminating the current prefetch upon detection of a phase change may reduce the number of prefetches which are no subsequently accessed. Accordingly, bandwidth to external memory is not consumed by the unused prefetches and hence may be available for other memory operations.

摘要翻译： 相变监视器监视一个或多个处理器资源以检测正在执行的程序中的相位变化。 相变监视器发信号通知预取单元以指示检测到的相位变化，并且还可以提供关于正被输入的相位（由相变监视器检测）的信息。 预取单元被配置为响应于检测到的相位变化而选择性地预取。 预取可以针对检测到的相位进行调整。 预取单元可以在检测到相位变化时禁用在前一阶段期间产生的当前预取，并且可以针对正被输入的阶段启动新的预取。 由于输入的相位可以在不同的数据集上操作，所以当前的预取可能不太可能是随后被访问的预取数据。 在检测到相位变化时终止当前预取可以减少不随后访问的预取数量。 因此，到外部存储器的带宽不被未使用的预取消耗，因此可用于其他存储器操作。

公开(公告)号：US5944816A

公开(公告)日：1999-08-31

申请号：US649809

申请日：1996-05-17

申请人： Drew J. Dutton ,  David S. Christie ,  Brian C. Barnes

发明人： Drew J. Dutton ,  David S. Christie ,  Brian C. Barnes

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/30

CPC分类号： G06F9/4812 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/462

摘要： A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently. Multiple tasks may be executed concurrently by the microprocessor in addition to executing multiple interrupt service routines concurrently. In still another embodiment, the microprocessor includes a primary context and multiple local context storages coupled to each of its execution units. A given execution unit may execute instructions referencing the primary context or the local context connected thereto.

摘要翻译： 提供了一种包括配置为存储多个上下文的上下文文件的微处理器。 微处理器可以执行多个线程，每个线程在微处理器内具有其自己的上下文。 在一个实施例中，本微处理器能够同时执行至少两个线程：任务和中断服务程序。 可以执行中断服务例程而不干扰任务的上下文，而不执行上下文保存操作。 相反，中断服务例程访问独立于任务上下文的上下文。 在另一个实施例中，上下文文件包括多个中断服务例程上下文。 多个ISR上下文存储允许同时执行嵌套中断。 在另一个实施例中，微处理器被配置为同时执行多个任务和多个中断服务程序。 除了同时执行多个中断服务程序之外，微处理器可以同时执行多个任务。 在另一个实施例中，微处理器包括耦合到其每个执行单元的主上下文和多个本地上下文存储器。 给定的执行单元可以执行引用主上下文或与其连接的本地上下文的指令。

公开(公告)号：US5835511A

公开(公告)日：1998-11-10

申请号：US649244

申请日：1996-05-17

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F11/10 ,  H03M13/09 ,  H03M13/00

CPC分类号： H03M13/095 ,  G06F11/10 ,  H03M13/098

摘要： A device and method that enables fault detection of control lines without additional fault detection lines. Prior to the transfer of a group of data, a control line is used to select whether even or odd parity is used on the group of data. After the data transfer, the same control signal is used at the destination device to select the type of parity used to check the validity of the data. If an error occurs on the control line that causes the state of the control line to change, the destination device will use the a different type of parity (even or odd parity) to check the validity of the group of data, and an error will be detected. In this manner, an error on the control line can be detected without additional parity signals.

摘要翻译： 一种能够在没有附加故障检测线路的情况下对控制线路进行故障检测的设备和方法。 在传送一组数据之前，使用控制线来选择是否在该组数据上使用偶校验或奇校验。 在数据传输之后，目的设备使用相同的控制信号来选择用于检查数据有效性的奇偶校验类型。 如果在控制线上出现错误，导致控制线的状态发生变化，目标设备将使用不同类型的奇偶校验（偶校验或奇校验）来检查数据组的有效性，错误将会 被检测。 以这种方式，可以在没有额外的奇偶校验信号的情况下检测到控制线上的错误。

公开(公告)号：US5799162A

公开(公告)日：1998-08-25

申请号：US716764

申请日：1996-09-23

申请人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

发明人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/26

CPC分类号： G06F9/382 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/321 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.

公开(公告)号：US5559975A

公开(公告)日：1996-09-24

申请号：US252030

申请日：1994-06-01

申请人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

发明人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/26

CPC分类号： G06F9/382 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/321 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.

公开(公告)号：US09372718B2

公开(公告)日：2016-06-21

申请号：US12510905

申请日：2009-07-28

申请人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

发明人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

IPC分类号： G06F9/46 ,  G06F9/52 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/468 ,  G06F9/52

摘要： A system and method for executing a transaction in a transactional memory system is disclosed. The system includes a processor of a plurality of processors coupled to shared memory, wherein the processor is configured to execute a section of code, including a plurality of memory access operations to the shared memory, as an atomic transaction relative to the execution of the plurality of processors. According to embodiments, the processor is configured to determine whether the memory access operations include any of a set of disallowed instructions, wherein the set includes one or more instructions that operate differently in a virtualized computing environment than in a native computing environment. If any of the memory access operations are ones of the disallowed instructions, then the processor aborts the transaction.

摘要翻译： 公开了一种在事务存储器系统中执行事务的系统和方法。 该系统包括耦合到共享存储器的多个处理器的处理器，其中处理器被配置为执行包括对共享存储器的多个存储器访问操作的代码段，作为相对于多个执行的执行的原子事务 的处理器。 根据实施例，处理器被配置为确定存储器访问操作是否包括一组不允许的指令中的任何一个，其中该集合包括在虚拟化计算环境中比在本机计算环境中不同地操作的一个或多个指令。 如果任何存储器访问操作是不允许的指令，则处理器中止该事务。