公开(公告)号：US5944816A

公开(公告)日：1999-08-31

申请号：US649809

申请日：1996-05-17

申请人： Drew J. Dutton ,  David S. Christie ,  Brian C. Barnes

发明人： Drew J. Dutton ,  David S. Christie ,  Brian C. Barnes

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/30

CPC分类号： G06F9/4812 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/462

摘要： A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently. Multiple tasks may be executed concurrently by the microprocessor in addition to executing multiple interrupt service routines concurrently. In still another embodiment, the microprocessor includes a primary context and multiple local context storages coupled to each of its execution units. A given execution unit may execute instructions referencing the primary context or the local context connected thereto.

摘要翻译： 提供了一种包括配置为存储多个上下文的上下文文件的微处理器。 微处理器可以执行多个线程，每个线程在微处理器内具有其自己的上下文。 在一个实施例中，本微处理器能够同时执行至少两个线程：任务和中断服务程序。 可以执行中断服务例程而不干扰任务的上下文，而不执行上下文保存操作。 相反，中断服务例程访问独立于任务上下文的上下文。 在另一个实施例中，上下文文件包括多个中断服务例程上下文。 多个ISR上下文存储允许同时执行嵌套中断。 在另一个实施例中，微处理器被配置为同时执行多个任务和多个中断服务程序。 除了同时执行多个中断服务程序之外，微处理器可以同时执行多个任务。 在另一个实施例中，微处理器包括耦合到其每个执行单元的主上下文和多个本地上下文存储器。 给定的执行单元可以执行引用主上下文或与其连接的本地上下文的指令。

公开(公告)号：US5819080A

公开(公告)日：1998-10-06

申请号：US582125

申请日：1996-01-02

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/30094 ,  G06F12/0804 ,  G06F12/0888 ,  G06F9/30185 ,  G06F9/383 ,  G06F9/3846

摘要： A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register override prefix byte which may be included with the instruction. Branch instructions may be scheduled distant from the instruction which sets the condition flags tested by the branch instruction. Numerous instructions may be placed between the two instructions, such that the condition flags may be available at the time the instruction is fetched. The branch instruction may be executed without stalling until the condition flags are available. In another embodiment, the branch prediction unit is configured to predict the direction a branch instruction may take according to a branch prediction scheme. Additionally, upon detection of a segment override prefix byte, the branch prediction unit uses an alternative branch prediction scheme. The alternative branch prediction scheme may be to predict the branch taken if a particular segment register override prefix byte is detected, and to predict the branch not taken if another particular segment register override prefix byte is detected.

摘要翻译： 提供了一种微处理器，其包括分支预测单元，该分支预测单元被配置为根据可能包含在该指令中的分段寄存器覆盖前缀字节来选择由分支指令使用的多组条件标志中的一个。 分支指令可以被调度为远离设置由分支指令测试的条件标志的指令。 可以在两个指令之间放置许多指令，使得条件标志在获取指令时可用。 分支指令可以在不停止的情况下执行，直到条件标志可用。 在另一实施例中，分支预测单元被配置为根据分支预测方案来预测分支指令可以采用的方向。 此外，在检测到段重写前缀字节时，分支预测单元使用替代分支预测方案。 替代分支预测方案可以是预测如果检测到特定分段寄存器覆盖前缀字节所采取的分支，并且如果检测到另一个特定分段寄存器覆盖前缀字节，则预测未采用的分支。

公开(公告)号：US5680578A

公开(公告)日：1997-10-21

申请号：US479782

申请日：1995-06-07

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F9/30185 ,  G06F9/34 ,  G06F9/3844

摘要： A microprocessor is provided which expands the functionality and/or performance of the implemented architecture in transparent and/or non-transparent ways. The microprocessor is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode and to use the prefix value to control internal and/or external functions. Additionally, the microprocessor may be configured to signal a change or modification of the normal execution of the instruction(s) which follow. Many embodiments are shown which use the segment override prefixes to expand the performance or capability of the microprocessor. Backward compatibility with older implementations of the x86 architecture may be maintained when implementing transparent embodiments.

摘要翻译： 提供了一种微处理器，其以透明和/或不透明的方式扩展了实施的架构的功能和/或性能。 微处理器被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段重写前缀，并且使用前缀值来控制内部和/或外部功能。 另外，微处理器可以被配置为发信号通知随后的指令的正常执行的改变或修改。 示出了使用段重写前缀来扩展微处理器的性能或能力的许多实施例。 在实现透明实施例时，可以维护与旧版本的x86架构的向后兼容性。

公开(公告)号：US5822778A

公开(公告)日：1998-10-13

申请号：US886421

申请日：1997-07-01

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/02

CPC分类号： G06F9/30138 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30185 ,  G06F9/342 ,  G06F9/3844

摘要： A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to control the selection of a bank of registers to use for the instruction operands. Each bank of registers includes the full complement of AMD 80x86 Series registers. Additional registers are available to a program other than the AMD 80x86 Series architecture specifies, but the instruction encoding is unchanged. Having more registers available to a program allows for more operands to be stored in the registers. Since registers are accessible in a shorter period of time than memory, operand access time is decreased.

摘要翻译： 提供了微处理器，其被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段超越前缀，并且使用前缀值或存储在相关联的段寄存器中的值来控制寄存器组的选择 用于指令操作数。 每个寄存器组包括AMD + Z 80x86系列寄存器的全套。 除AMD + Z 80x86系列架构外，其他寄存器可用于指定，但指令编码不变。 有更多的寄存器可用于程序允许更多的操作数存储在寄存器中。 由于寄存器在比内存更短的时间段内可访问，所以操作数访问时间减少。

公开(公告)号：US5768574A

公开(公告)日：1998-06-16

申请号：US914698

申请日：1997-08-19

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30094 ,  G06F9/30185 ,  G06F9/34 ,  G06F9/3844

摘要： A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to selectively enable condition flag modification for instructions. An instruction which modifies the condition flags and a branch instruction intended to branch based on the condition flags set by the instruction may be separated by numerous instructions which do not modify the condition flags. When the branch instruction is decoded, the condition flags it depends on may already be available. In another embodiment of the present microprocessor, the segment register override bytes are used to select between multiple sets of condition flags. Multiple conditions may be retained by the microprocessor for later examination. Conditions which a program utilizes multiple times in a program may be maintained while other conditions may be generated and utilized.

摘要翻译： 提供了微处理器，其被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段超越前缀，并且使用前缀值或存储在相关联的段寄存器中的值来选择性地启用用于指令的条件标志修改。 根据指令设定的条件标志修改条件标志和分支指令的指令可以被不修改条件标志的许多指令分开。 当分支指令被解码时，它所依赖的条件标志可能已经可用。 在本微处理器的另一实施例中，段寄存器覆盖字节用于在多组条件标志之间进行选择。 微处理器可以保留多个条件供以后检查。 在程序中利用多次的程序的条件可以被保持，而可以产生和利用其他条件。

公开(公告)号：US08239603B2

公开(公告)日：2012-08-07

申请号：US11417391

申请日：2006-05-03

申请人： Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

发明人： Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

IPC分类号： G06F13/40

CPC分类号： G06F13/4027

摘要： A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

摘要翻译： 一种包括序列化二次总线架构的系统。 该系统可以包括LPC总线，I / O控制器，串行化辅助总线和至少一个从设备。 LPC总线可以连接到I / O控制器，并且至少一个从设备可以经由串行辅助总线连接到I / O控制器。 串行次级总线相对于LPC总线的引脚数量减少。 I / O控制器可以从LPC总线接收总线事务。 I / O控制器可以通过辅助总线将LPC总线事务转换和转发到至少一个设备。 I / O控制器可以包括处理单元。 处理单元可以启动用于至少一个从设备的总线事务。 I / O控制器还可以包括总线仲裁单元。 总线仲裁单元可以仲裁处理单元和LPC总线之间的辅助总线的所有权。

公开(公告)号：US6047350A

公开(公告)日：2000-04-04

申请号：US989329

申请日：1997-12-11

申请人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

发明人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

IPC分类号： G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

CPC分类号： H04N21/238 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4027

摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

摘要翻译： 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的字节分片逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片多媒体总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：US5923887A

公开(公告)日：1999-07-13

申请号：US650570

申请日：1996-05-20

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing units (CPUs). At least one CPU and a main memory system are coupled to a host bus. A bus bridge device couples the host bus to the expansion bus. At least one I/O device is coupled to the expansion bus and generates an interrupt request signal. The bus bridge and other bus devices may also generate interrupt request signals. A programmable interrupt controller receives the interrupt requests and provides processor interrupt signals as well as information regarding resource requirements necessary for servicing the interrupts to the one or more CPUs. The programmable interrupt controller also receives interrupt acknowledge signals from the one or more CPUs.

摘要翻译： 一种改进的可编程中断控制器，用于包括一个或多个中断服务提供商（ISP）的计算机系统，通常是中央处理单元（CPU）。 至少一个CPU和主存储器系统耦合到主机总线。 总线桥装置将主机总线耦合到扩展总线。 至少一个I / O设备被耦合到扩展总线并产生中断请求信号。 总线桥和其他总线设备也可能产生中断请求信号。 可编程中断控制器接收中断请求并提供处理器中断信号以及关于维护一个或多个CPU的中断所需的资源需求的信息。 可编程中断控制器还从一个或多个CPU接收中断确认信号。

公开(公告)号：US5317715A

公开(公告)日：1994-05-31

申请号：US911783

申请日：1992-07-10

申请人： William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

发明人： William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F13/00 ,  G06F13/23

CPC分类号： G06F13/4013 ,  G06F13/28

摘要： Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

摘要翻译： 公开了用于向简化指令集计算机（RISC）系统的本地总线传输数据的方法和装置，包括至少一个中央处理器（“CPU”）的第一组高性能设备， 和远程总线，第二组相对较低性能的设备以不限制RISC处理器性能的方式连接到该远程总线。 根据本发明的优选实施例，公开了一种RISC架构，其包括新颖的数据传输控制器（“DTC”）或一组DTC，适用于在高性能本地总线与一个或多个本地总线之间执行上述数据传输功能 通常具有不同（和较低）性能特征的完整子系统或外设的远程总线。 由此产生的RISC节点允许商业化的外围设备和子系统与高性能RISC处理器配合使用，而不会限制RISC系统的性能。

公开(公告)号：US08149001B2

公开(公告)日：2012-04-03

申请号：US12359056

申请日：2009-01-23

申请人： Simeon K. Iliev ,  Drew J. Dutton

发明人： Simeon K. Iliev ,  Drew J. Dutton

IPC分类号： G01R27/26

CPC分类号： G06K9/0002

摘要： Low cost fingerprint system having a single chip solution includes a circuit board, a fingerprint sensor array fabricated onto a first surface of the circuit board, and an integrated circuit die for processing information received from the fingerprint sensor array is mounted directly to a second surface of the circuit board. The integrated circuit die may be electrically connected to the sensor by, for example, vias in the circuit board.

摘要翻译： 具有单芯片解决方案的低成本指纹系统包括电路板，制造在电路板的第一表面上的指纹传感器阵列和用于处理从指纹传感器阵列接收的信息的集成电路管芯直接安装在第二表面 电路板。 集成电路管芯可以通过例如电路板中的通孔电连接到传感器。