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    Field Effect Transistor Device and Fabrication
    61.
    发明申请
    Field Effect Transistor Device and Fabrication 有权
    场效应晶体管器件和制造

    公开(公告)号：US20120286366A1

    公开(公告)日：2012-11-15

    申请号：US13554294

    申请日：2012-07-20

    Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

    IPC: H01L27/092

    CPC classification number: H01L29/42368 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66477

    Abstract: In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.

    Abstract translation: 在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层 第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

    Field Effect Transistor Device with Shaped Conduction Channel
    62.
    发明申请
    Field Effect Transistor Device with Shaped Conduction Channel 有权
    具有形状导通通道的场效应晶体管器件

    公开(公告)号：US20120280279A1

    公开(公告)日：2012-11-08

    申请号：US13551164

    申请日：2012-07-17

    Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66621

    Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

    Abstract translation: 场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料， 填充空腔的金属栅极材料，源极区域和漏极区域。

    THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
    63.
    发明申请
    THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION 有权
    通过门电介质堆栈修正进行阈值电压调节

    公开(公告)号：US20120108017A1

    公开(公告)日：2012-05-03

    申请号：US13347014

    申请日：2012-01-10

    Applicant: Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

    Inventor： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

    IPC: H01L21/782 ,  H01L21/8238

    CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

    Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

    Abstract translation: 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

    Diffusion sidewall for a semiconductor structure
    64.
    发明授权
    Diffusion sidewall for a semiconductor structure 有权
    用于半导体结构的扩散侧壁

    公开(公告)号：US08105893B2

    公开(公告)日：2012-01-31

    申请号：US12621216

    申请日：2009-11-18

    Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

    IPC: H01L21/8238

    CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

    Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.

    Abstract translation: 在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁 区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

    SELF-ALIGNED CONTACTS
    66.
    发明申请
    SELF-ALIGNED CONTACTS 有权
    自对准联系人

    公开(公告)号：US20110248362A1

    公开(公告)日：2011-10-13

    申请号：US12755752

    申请日：2010-04-07

    Applicant: Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

    Inventor： Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

    Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

    Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

    GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE
    67.
    发明申请
    GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE 有权
    基于GRAPHENE的三维集成电路设备

    公开(公告)号：US20110215300A1

    公开(公告)日：2011-09-08

    申请号：US12719058

    申请日：2010-03-08

    Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

    IPC: H01L27/088 ,  H01L21/8256

    CPC classification number: H01L27/0688 ,  H01L29/1606 ,  Y10S977/755

    Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

    Abstract translation: 三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

    Method to fabricate a vertical transistor having an asymmetric gate with two conductive layers having different work functions
    69.
    发明授权
    Method to fabricate a vertical transistor having an asymmetric gate with two conductive layers having different work functions 有权
    制造具有不对称栅极的垂直晶体管的方法，具有不同功函数的两个导电层

    公开(公告)号：US09142660B2

    公开(公告)日：2015-09-22

    申请号：US13611113

    申请日：2012-09-12

    Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66

    CPC classification number: H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

    Abstract: A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

    Abstract translation: 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。

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