公开(公告)号：US06380087B1

公开(公告)日：2002-04-30

申请号：US09596901

申请日：2000-06-19

申请人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L24/02 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  Y10S438/926

摘要： A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.

摘要翻译： 一种制造具有至少一个集成电路的半导体晶片的方法，所述方法包括以下步骤。 提供了至少具有上介电层和下电介质层的半导体晶片结构。 该半导体晶片结构具有焊盘区域和互连区域。 具有第一宽度的至少一个有源互连通过电介质层形成在互连区域中。 通过电介质层的一部分，在焊盘区域中形成多个具有第二宽度的相邻虚拟插头。 对半导体晶片结构进行图案化和蚀刻，以形成通过上部电介质层的沟槽。 沟槽围绕至少一个有源互连和虚拟插头中的每一个，由此相邻虚拟插头之间的上部电介质层被去除。 金属化层沉积在下电介质层上，至少填充到剩余的上电介质层的上表面上的沟槽。 金属化层被平坦化以去除在焊盘区域内形成连续接合焊盘的多余的金属化层，并且包括多个相邻的虚设插头，从而形成包括至少一个相应的有源互连的至少一个镶嵌结构。

公开(公告)号：US08394724B2

公开(公告)日：2013-03-12

申请号：US11843629

申请日：2007-08-22

申请人： Hai Cong ,  Wei Loong Loh ,  Krishan Gopal ,  Xin Zhang ,  Mei Sheng Zhou ,  Pradeep Ramachandramurthy Yelehanka

发明人： Hai Cong ,  Wei Loong Loh ,  Krishan Gopal ,  Xin Zhang ,  Mei Sheng Zhou ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L21/312

CPC分类号： H01L21/32137 ,  H01L21/32139

摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

摘要翻译： 用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

公开(公告)号：US08324011B2

公开(公告)日：2012-12-04

申请号：US11853156

申请日：2007-09-11

申请人： Chyiu Hyia Poon ,  Alex See ,  Mei Sheng Zhou

发明人： Chyiu Hyia Poon ,  Alex See ,  Mei Sheng Zhou

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/268

摘要： The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

摘要翻译： 本发明提供了一种通过向半导体结构施加温度相关的相位开关层来退火半导体的方法。 温度相关的相位开关层在预定温度下将相从非晶形变化为结晶。 当半导体结构退火时，电磁辐射在到达半导体结构之前通过温度相关的相位开关层。 当达到期望的退火温度时，温度相关的相位开关层基本上阻止电磁辐射到达半导体结构。 结果，半导体在晶片上以一致的温度退火。 温度相关的相位开关层改变相位的温度可以通过离子注入工艺来控制。

公开(公告)号：US20110281410A1

公开(公告)日：2011-11-17

申请号：US13190805

申请日：2011-07-26

申请人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US08012839B2

公开(公告)日：2011-09-06

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US07966142B2

公开(公告)日：2011-06-21

申请号：US12103690

申请日：2008-04-15

申请人： Wen Zhan Zhou ,  Zheng Zou ,  Jasper Goh ,  Mei Sheng Zhou

发明人： Wen Zhan Zhou ,  Zheng Zou ,  Jasper Goh ,  Mei Sheng Zhou

IPC分类号： G01D21/00 ,  G06F19/00

CPC分类号： H01L22/12 ,  G01B21/045 ,  G01B2210/56 ,  H01L22/20

摘要： A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.

摘要翻译： 描述了一种评估测量工具精度的方法。 多变量回归用于定义计量工具的准确性，以便考虑不同测量参数之间的相互作用。 被测量的测量工具（MTUT）和参考计量工具（RMT）用于测量一组测试曲线。 MTUT测量测试配置文件，以生成第一个测量参数的MTUT数据集。 RMT测量测试配置文件以生成用于第一测量参数的RMT数据集和至少第二测量参数。 然后执行多变量回归以为数据集生成最佳拟合平面。 测定系数（R2值）表示MTUT的精度指标。

公开(公告)号：US07776699B2

公开(公告)日：2010-08-17

申请号：US12025788

申请日：2008-02-05

申请人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L29/778

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636

摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

摘要翻译： 一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变 底物。

公开(公告)号：US20090218597A1

公开(公告)日：2009-09-03

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US20090053864A1

公开(公告)日：2009-02-26

申请号：US11844074

申请日：2007-08-23

申请人： Jinping Liu ,  Alex K.H. See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K.H. See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02609 ,  H01L29/045

摘要： A method for fabricating a semiconductor structure having heterogeneous crystalline orientations by forming a region including a semiconductor material having a specified crystalline orientation using an epitaxial buffer overlying a semiconductor substrate. The buffer provides a transfer body such that the semiconductor material has a crystalline orientation that differs from the crystalline orientation of a semiconductor region underlying the buffer. The method also includes fabricating a semiconductor structure having a p-type device region and an n-type device region, where a supporting semiconductor substrate is either n-type or p-type and where the semiconductor material is separated from the substrate by a buffer and has a crystalline orientation that differs from the crystalline orientation of the substrate.

摘要翻译： 一种通过使用覆盖在半导体衬底上的外延缓冲层形成包含具有指定结晶取向的半导体材料的区域来制造具有异质结晶取向的半导体结构的方法。 缓冲器提供转移体，使得半导体材料具有不同于缓冲器下面的半导体区域的晶体取向的结晶取向。 该方法还包括制造具有p型器件区域和n型器件区域的半导体结构，其中支持半导体衬底是n型或p型，并且半导体材料通过缓冲器与衬底分离 并且具有不同于衬底的晶体取向的结晶取向。

公开(公告)号：US5795699A

公开(公告)日：1998-08-18

申请号：US679858

申请日：1996-07-15

申请人： Mei Sheng Zhou ,  Ron-Fu Chu

发明人： Mei Sheng Zhou ,  Ron-Fu Chu

IPC分类号： G03F7/09 ,  G03F7/16 ,  G03C5/00

CPC分类号： G03F7/091 ,  G03F7/165 ,  Y10S438/939

摘要： A method for forming upon a reflective layer, such as a reflective conducting layer, within an integrated circuit an Anti-Reflective Coating (ARC) which simultaneously possesses adhesion promotion characteristics for an organic layer to be formed upon the reflective layer. There is first formed upon a semiconductor wafer a reflective integrated circuit layer which may be a hydrophilic reflective integrated circuit layer or a hydrophobic integrated circuit layer. The semiconductor wafer is then immersed into and withdrawn from a Langmuir trough having formed therein a Langmuir-Blodgett (LB) monolayer film of a dye surfactant molecule ordered upon a surface of water. Upon withdrawing the wafer from the Langmuir trough, there is formed upon the reflective integrated circuit layer an ordered LB film of the dye surfactant molecule. The chromophore groups within the dye surfactant molecule and ordered LB film provide ARC characteristics to the reflective layer.

摘要翻译： 一种用于在集成电路内的反射层（例如反射导电层）上形成抗反射涂层（ARC）的方法，该抗反射涂层同时具有将在反射层上形成的有机层的粘附促进特性。 首先在半导体晶片上形成反射集成电路层，反射集成电路层可以是亲水反射集成电路层或疏水性集成电路层。 然后将半导体晶片浸入Langmuir槽中并从Langmuir槽中取出，Langmuir槽中形成了在水表面上排列的染料表面活性剂分子的Langmuir-Blodgett（LB）单层膜。 当从Langmuir槽中取出晶片时，在反射集成电路层上形成染料表面活性剂分子的有序LB膜。 染料表面活性剂分子内的发色团和有序的LB膜为反射层提供ARC特性。