公开(公告)号：US09245887B2

公开(公告)日：2016-01-26

申请号：US13955796

申请日：2013-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Hui-Zhong Zhuang ,  Shang-Chih Hsieh ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/092 ,  H01L27/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/092 ,  G06F17/5068 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.

Abstract translation: 集成电路布局包括第一有源区，第二有源区，第一PODE（OD边缘上的poly），第二PODE，第一晶体管和第二晶体管。 在第一有源区上的第一晶体管包括栅电极，源极区和漏极区。 在第二有源区上的第二晶体管包括栅电极，源极区和漏极区。 第一有源区和第二有源区相邻并且彼此电断开。 第一PODE和第二PODE位于第一有源区和第二有源区的相邻相邻边缘上。 第一和第二晶体管的源极区分别与第一PODE和第二PODE相邻。 第一PODE和第二PODE夹在第一晶体管和第二晶体管的源极区之间。

公开(公告)号：US12277378B2

公开(公告)日：2025-04-15

申请号：US18362946

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Li-Chun Tien ,  Shun Li Chen ,  Lee-Chung Lu

IPC: G06F30/398 ,  G06F30/392 ,  H01L27/02 ,  H01L27/118

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

公开(公告)号：US12266594B2

公开(公告)日：2025-04-01

申请号：US18517298

申请日：2023-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L23/48 ,  H01L21/768

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

公开(公告)号：US12224753B2

公开(公告)日：2025-02-11

申请号：US18365199

申请日：2023-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jin-Wei Xu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H03K3/356

Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

公开(公告)号：US12216978B2

公开(公告)日：2025-02-04

申请号：US17225903

申请日：2021-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Anurag Verma ,  Meng-Kai Hsu ,  Chih-Wei Chang ,  Sang-Chi Huang ,  Wei-Ling Chang ,  Hui-Zhong Zhuang

IPC: G06F30/3953 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A layout method and a semiconductor device are disclosed. The layout method includes: generating a design layout by placing a cell, wherein the cell includes: a first conductive segment overlapping a source/drain region and disposed immediately adjacent to a first power rail, wherein the first conductive segment has a length substantially equal to a cell length; a second conductive segment; and a third conductive segment between the first and second conductive segments. The layout method further includes: providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments are aligned in a first direction.

公开(公告)号：US12176394B2

公开(公告)日：2024-12-24

申请号：US18358694

申请日：2023-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L29/06 ,  G06F30/392 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

公开(公告)号：US12164853B2

公开(公告)日：2024-12-10

申请号：US17574048

申请日：2022-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Anurag Verma ,  Chi-Chun Liang ,  Meng-Kai Hsu ,  Cheng-Yu Lin ,  Pochun Wang ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  G06F30/394 ,  G06F119/18

Abstract: The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

公开(公告)号：US12124785B2

公开(公告)日：2024-10-22

申请号：US18448115

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Hong Gao ,  Hui-Zhong Zhuang

IPC: G06F30/30 ,  G06F30/392 ,  H01L21/04 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L21/041 ,  H01L27/0207

Abstract: A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.

公开(公告)号：US12107581B2

公开(公告)日：2024-10-01

申请号：US18362916

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

IPC: H03K3/037 ,  G06F1/12 ,  H03K19/20

CPC classification number: H03K3/037 ,  G06F1/12 ,  H03K19/20

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

公开(公告)号：US12073170B2

公开(公告)日：2024-08-27

申请号：US18354423

申请日：2023-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H03K19/094 ,  H01L23/522

CPC classification number: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

Abstract: An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.