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    Integrated circuit including super via and method of making
    68.
    发明授权
    Integrated circuit including super via and method of making 有权

    公开(公告)号：US11735517B2

    公开(公告)日：2023-08-22

    申请号：US17590439

    申请日：2022-02-01

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Kam-Tou Sio ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

    CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/528

    摘要： A method including depositing a first dielectric layer over a first conductive line. The method further includes forming a first opening in the first dielectric layer. The method further includes filling the first opening with a first conductive material to define a second conductive line. The method further includes depositing a second dielectric layer over the first dielectric layer. The method further includes forming a second opening in the second dielectric layer. The method further includes filling the second opening with a second conductive material to define a third conductive line. The method further includes forming a supervia opening in the first dielectric layer and the second dielectric layer. The method further includes filling the supervia opening with a third conductive material to define a supervia, wherein the supervia directly connects to the first conductive line and the third conductive line.

    Integrated circuit, system and method of forming same
    69.
    发明授权
    Integrated circuit, system and method of forming same 有权

    公开(公告)号：US11626369B2

    公开(公告)日：2023-04-11

    申请号：US17237530

    申请日：2021-04-22

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

    IPC分类号： H01L21/8238 ,  H01L23/528 ,  H01L27/092

    摘要： An integrated circuit includes a first, second and third active region and a first, second and third conductive line. The first, second and third active regions extend in a first direction, and are on a first level of a front-side of a substrate. The second active region is between the first active region and the third active region. The first and second conductive line extend in the first direction, and are on a second level of a back-side of the substrate. The first conductive line is between the first and second active region. The second conductive line is between the second and third active region. The third conductive line extends in the second direction, is on a third level of the back-side of the substrate, overlaps the first and second conductive line, and electrically couples the first and second active regions.

    Method of manufacturing semiconductor device
    70.
    发明授权
    Method of manufacturing semiconductor device 有权

    公开(公告)号：US11569167B2

    公开(公告)日：2023-01-31

    申请号：US17115422

    申请日：2020-12-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Shih-Wei Peng ,  Hui-Ting Yang ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L27/02 ,  H01L23/48

    摘要： A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.