公开(公告)号：US11362047B2

公开(公告)日：2022-06-14

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20210327794A1

公开(公告)日：2021-10-21

申请号：US17233110

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

公开(公告)号：US20210327790A1

公开(公告)日：2021-10-21

申请号：US17233205

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

公开(公告)号：US20210159403A1

公开(公告)日：2021-05-27

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  H01L43/06 ,  G01R15/20 ,  H01L23/495 ,  G01R33/07

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US09941228B2

公开(公告)日：2018-04-10

申请号：US15497024

申请日：2017-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajen Manicon Murugan ,  Minhong Mi ,  Gary Paul Morrison ,  Jie Chen ,  Kenneth Robert Rhyner ,  Stanley Craig Beddingfield ,  Chittranjan Mohan Gupta ,  Django Earl Trombley

IPC: H01Q1/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H05K1/02 ,  H01Q1/22 ,  H01Q1/32 ,  H01Q23/00

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1423 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30111 ,  H01Q1/2283 ,  H01Q1/3233 ,  H01Q23/00 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/181 ,  H05K2201/09609 ,  H05K2201/10734 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond ball grid array package comprises a solder ball array, a millimeter wave transmit channel, and a millimeter wave receive channel, wherein each millimeter wave transmit and receive channel electrically couples the IC die to a signal ball of the solder ball array and is configured to resonate at an operating frequency band of the millimeter wave IC chip.