-
公开(公告)号:US10747103B2
公开(公告)日:2020-08-18
申请号:US16228339
申请日:2018-12-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yun-Yue Lin , Hsuan-Chen Chen , Chih-Cheng Lin , Hsin-Chang Lee , Yao-Ching Ku , Wei-Jen Lo , Anthony Yen , Chin-Hsiang Lin , Mark Chien
Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
-
公开(公告)号:US10001701B1
公开(公告)日:2018-06-19
申请号:US15380121
申请日:2016-12-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pei-Cheng Hsu , Hsin-Chang Lee , Yun-Yue Lin , Hsuan-Chen Chen , Hsuan-I Wang , Anthony Yen
Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
-
63.
公开(公告)号:US09530200B2
公开(公告)日:2016-12-27
申请号:US14309980
申请日:2014-06-20
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Wen-Chang Hsueh , Chia-Jen Chen , Hsin-Chang Lee
CPC classification number: G06T7/0006 , G02B21/0016 , G02B21/367 , G06T7/0004 , G06T7/13 , G06T2207/10061 , G06T2207/30148 , H01L22/12
Abstract: A method and a system for inspection of a patterned structure are provided. In various embodiments, the method for inspection of a patterned structure includes transferring the patterned structure into a microscope. The method further includes acquiring a top-view image of the patterned structure by the microscope. The method further includes transferring the patterned structure out of the microscope and exporting the top-view image to an image analysis processor. The method further includes measuring a difference between a contour of the top-view image and a predetermined layout of the patterned structure by the image analysis processor.
Abstract translation: 提供了一种用于检查图案结构的方法和系统。 在各种实施例中,用于检查图案化结构的方法包括将图案化结构转移到显微镜中。 该方法还包括通过显微镜获取图案化结构的顶视图。 该方法还包括将图案化结构转移出显微镜并将顶视图输出到图像分析处理器。 该方法还包括通过图像分析处理器测量顶视图像的轮廓与图案化结构的预定布局之间的差异。
-
公开(公告)号:US11815804B2
公开(公告)日:2023-11-14
申请号:US17481673
申请日:2021-09-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Ping-Hsun Lin , Pei-Cheng Hsu , Ching-Fang Yu , Ta-Cheng Lien , Chia-Jen Chen , Hsin-Chang Lee
IPC: G03F1/24
CPC classification number: G03F1/24
Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.
-
公开(公告)号:US11768431B2
公开(公告)日:2023-09-26
申请号:US17094727
申请日:2020-11-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Chih-Cheng Chen , ShinAn Ku , Ting-Hao Hsu , Hsin-Chang Lee
CPC classification number: G03F1/22 , G01B11/22 , G01B11/24 , G01J3/0208
Abstract: A method of scanning a substrate and determining scratches of the substrate includes transmitting a converging beam of light that comprises multiple wavelengths to the substrate. Each wavelength of the multiple wavelengths focuses at a different distance in a focus interval around and including a surface of the substrate. The method also includes receiving reflected light from the surface of the substrate and determining a height or depth of the surface of the substrate based on a wavelength of the reflected light having a highest intensity.
-
公开(公告)号:US11592737B2
公开(公告)日:2023-02-28
申请号:US17103023
申请日:2020-11-24
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Hung-Yi Tsai , Wei-Che Hsieh , Ta-Cheng Lien , Hsin-Chang Lee , Ping-Hsun Lin , Hao-Ping Cheng , Ming-Wei Chen , Szu-Ping Tsai
IPC: G03F1/24
Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
-
公开(公告)号:US11448956B2
公开(公告)日:2022-09-20
申请号:US16562400
申请日:2019-09-05
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Ching-Huang Chen , Chi-Yuan Sun , Hua-Tai Lin , Hsin-Chang Lee , Ming-Wei Chen
IPC: G03F1/24 , H01L21/033
Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).
-
公开(公告)号:US11294271B2
公开(公告)日:2022-04-05
申请号:US16863939
申请日:2020-04-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wen-Chang Hsueh , Hsin-Chang Lee , Ta-Cheng Lien
IPC: G03F1/24
Abstract: A method for forming an extreme ultraviolet photolithography mask includes forming a reflective multilayer, forming a buffer layer on the reflective multilayer, and forming an absorption layer on the reflective multilayer. Prior to patterning the absorption layer, an outer portion of the absorption layer is removed. Photoresist is then deposited on the top surface of the absorption layer and on sidewalls of the absorption layer. The photoresist is then patterned, and the absorption layer is etched with a plasma etching process in the presence of the patterned photoresist. The presence of the photoresist on the sidewalls of the absorption layer during the plasma etching process helps to improve uniformity in the etching of the absorption layer during the plasma etching process.
-
公开(公告)号:US11287754B2
公开(公告)日:2022-03-29
申请号:US17129841
申请日:2020-12-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Ming-Wei Chen , Hsin-Chang Lee , Ping-Hsun Lin
IPC: G03F7/20
Abstract: A mask for cleaning a lithography apparatus includes a mask substrate and a coating provided on a surface of the mask substrate. The coating is configured to trap particulate contaminant matter from the lithography apparatus. A method of cleaning a lithography tool is also provided preparing a cleaning mask including a particle trapping layer formed on a substrate. The method includes transferring the cleaning mask through a mask transferring route of the lithography tool. Subsequently, the method includes analyzing a particle trapped by the particle trapping layer.
-
公开(公告)号:US11249384B2
公开(公告)日:2022-02-15
申请号:US16441700
申请日:2019-06-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Pei-Cheng Hsu , Chi-Ping Wen , Tzu Yi Wang , Ta-Cheng Lien , Hsin-Chang Lee
IPC: G03F1/22
Abstract: A method of manufacturing an extreme ultraviolet (EUV) lithography mask includes forming an image pattern in an absorption layer of EUV mask blank. The EUV mask blank includes: a multilayer stack including alternating molybdenum (Mo) and silicon (Si) layers disposed over a first surface of a mask substrate, a capping layer disposed over the multilayer stack, and an absorption layer disposed over the capping layer. A border region surrounds the image pattern having a trench wherein the absorption layer, the capping layer and at least a portion of the multilayer stack are etched. Concave sidewalls are formed in the border region or an inter-diffused portion is formed in the multilayer stack of the trench.
-
-
-
-
-
-
-
-
-