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公开(公告)号：US20210208505A1
公开(公告)日：2021-07-08
申请号：US17206722
申请日：2021-03-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shinn-Sheng Yu , Ching-Fang Yu , Wen-Chuan Wang , Ting-Hao Hsu , Sheng-Chi Chin , Anthony Yen
Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
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公开(公告)号：US10747103B2
公开(公告)日：2020-08-18
申请号：US16228339
申请日：2018-12-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yun-Yue Lin , Hsuan-Chen Chen , Chih-Cheng Lin , Hsin-Chang Lee , Yao-Ching Ku , Wei-Jen Lo , Anthony Yen , Chin-Hsiang Lin , Mark Chien
Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
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公开(公告)号：US10001701B1
公开(公告)日：2018-06-19
申请号：US15380121
申请日：2016-12-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Pei-Cheng Hsu , Hsin-Chang Lee , Yun-Yue Lin , Hsuan-Chen Chen , Hsuan-I Wang , Anthony Yen
Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
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公开(公告)号：US20160109798A1
公开(公告)日：2016-04-21
申请号：US14980469
申请日：2015-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Tsung Shih , Tien-Hsi Lee , Chia-Jen Chen , Shang-Chieh Chien , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
IPC: G03F1/64
CPC classification number: G03F1/64 , B29C71/02 , B29C2071/022 , G03F1/62 , G03F7/2002
Abstract: The present disclosure relates to a method of forming an extreme ultraviolet (EUV) pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate. A pellicle frame is attached to an upper surface of the substrate, and the substrate is cleaved along the cleaving plane to form a pellicle film attached to the pellicle frame. The method forms the pellicle without using a support structure, which may block EUV radiation and cause substantial non-uniformities in the intensity of EUV radiation incident on an EUV reticle.
Abstract translation: 本发明涉及一种形成极紫外（EUV）防护薄膜组件的方法，所述防护薄膜组件具有连接到没有支撑网的防护薄膜框架上的防护薄膜组件及相关装置。 在一些实施例中，通过在衬底内形成切割平面来执行该方法。 防护薄膜组件框架附接到基板的上表面，并且基板沿着切割平面被切割以形成附着到防护薄膜框架上的防护薄膜组件。 该方法不使用支撑结构形成防护薄膜组件，其可以阻挡EUV辐射并且在EUV掩模版上入射的EUV辐射的强度引起实质上的不均匀性。
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公开(公告)号：US11092555B2
公开(公告)日：2021-08-17
申请号：US16933067
申请日：2020-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Lin Louis Chang , Shang-Chieh Chien , Shang-Ying Wu , Li-Kai Cheng , Tzung-Chi Fu , Bo-Tsun Liu , Li-Jui Chen , Po-Chung Cheng , Anthony Yen , Chia-Chen Chen
IPC: G01N21/88 , G01N21/954 , G03F7/20 , H01L21/027 , G01N21/956 , G01N21/94
Abstract: A single-shot metrology for direct inspection of an entirety of the interior of an EUV vessel is provided. An EUV vessel including an inspection tool integrated with the EUV vessel is provided. During an inspection process, the inspection tool is moved into a primary focus region of the EUV vessel. While the inspection tool is disposed at the primary focus region and while providing a substantially uniform and constant light level to an interior of the EUV vessel by way of an illuminator, a panoramic image of an interior of the EUV vessel is captured by way of a single-shot of the inspection tool. Thereafter, a level of tin contamination on a plurality of components of the EUV vessel is quantified based on the panoramic image of the interior of the EUV vessel. The quantified level of contamination is compared to a KPI, and an OCAP may be implemented.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10162257B2
公开(公告)日：2018-12-25
申请号：US15380717
申请日：2016-12-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Cheng Lu , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
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7.发明申请公开(公告)号：US20180173089A1
公开(公告)日：2018-06-21
申请号：US15380717
申请日：2016-12-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Cheng Lu , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
CPC classification number: G03F1/26 , G03F7/70033 , G03F7/70191 , G03F7/70308
Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
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8.发明申请公开(公告)号：US20180149959A1
公开(公告)日：2018-05-31
申请号：US15670183
申请日：2017-08-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yun-Yue Lin , Hsin-Chang Lee , Chia-Jen Chen , Chih-Cheng Lin , Anthony Yen , Chin-Hsiang Lin
Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.
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9.发明授权公开(公告)号：US09134604B2
公开(公告)日：2015-09-15
申请号：US14015885
申请日：2013-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., LTD
Inventor： Chih-Tsung Shih , Hsin-Chieh Yao , Shinn-Sheng Yu , Jeng-Horng Chen , Chung-Ju Lee , Anthony Yen
Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.
Abstract translation: 提供含Cu材料作为EUV掩模的吸收层。 利用含Cu材料的吸收层，根据本公开的各种实施方案，仅通过吸收层的厚度仅为30nm可以实现70nm厚的TaBN中的常规吸收体的相同的光刻性能。 此外，可以减少193-257nm的辐射光的带外（OOB）光斑，以获得更好的光刻性能。
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10.发明申请公开(公告)号：US20150064611A1
公开(公告)日：2015-03-05
申请号：US14015885
申请日：2013-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
Inventor： Chih-Tsung Shih , Hsin-Chieh Yao , Shinn-Sheng Yu , Jeng-Horng Chen , Chung-Ju Lee , Anthony Yen
Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.
Abstract translation: 提供含Cu材料作为EUV掩模的吸收层。 利用含Cu材料的吸收层，根据本公开的各种实施方案，仅通过吸收层的厚度仅为30nm可以实现70nm厚度的TaBN中的常规吸收体的相同的光刻性能。 此外，可以减少193-257nm的辐射光的带外（OOB）光斑，以获得更好的光刻性能。
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