公开(公告)号：US11830773B2

公开(公告)日：2023-11-28

申请号：US17006161

申请日：2020-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Wei Lee ,  Pang-Yen Tsai ,  Tsungyu Hung ,  Huang-Lin Chao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823431 ,  H01L21/02579 ,  H01L21/762 ,  H01L21/76275 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0665 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.

公开(公告)号：US11752592B2

公开(公告)日：2023-09-12

申请号：US17377759

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Liao ,  Chen-Hao Wu ,  An-Hsuan Lee ,  Huang-Lin Chao

IPC: B24B53/017 ,  B24B57/02

CPC classification number: B24B53/017 ,  B24B57/02

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

公开(公告)号：US20230282729A1

公开(公告)日：2023-09-07

申请号：US17662545

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chun-Da Liao ,  Cheng-Lung Hung ,  Yan-Ming Tsai ,  Harry Chien ,  Huang-Lin Chao ,  Weng Chang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/41791

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

公开(公告)号：US11621338B2

公开(公告)日：2023-04-04

申请号：US17228415

申请日：2021-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.

公开(公告)号：US20230021172A1

公开(公告)日：2023-01-19

申请号：US17377759

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung LIAO ,  Chen-Hao Wu ,  An-Hsuan Lee ,  Huang-Lin Chao

IPC: B24B53/017 ,  B24B57/02

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

公开(公告)号：US20220351976A1

公开(公告)日：2022-11-03

申请号：US17378017

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Huang-Lin Chao ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/40 ,  H01L27/092

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nano structures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; and depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.

公开(公告)号：US20220254927A1

公开(公告)日：2022-08-11

申请号：US17470548

申请日：2021-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Sheng-Tsung Wang ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L23/48 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.

公开(公告)号：US20210351278A1

公开(公告)日：2021-11-11

申请号：US17228415

申请日：2021-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.

公开(公告)号：US11139397B2

公开(公告)日：2021-10-05

申请号：US16572255

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.

公开(公告)号：US20210171800A1

公开(公告)日：2021-06-10

申请号：US17175986

申请日：2021-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsuan Lee ,  Shen-Nan Lee ,  Chen-Hao Wu ,  Chun-Hung Liao ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: C09G1/02 ,  H01L21/321 ,  H01L21/762

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.