公开(公告)号：US11854988B2

公开(公告)日：2023-12-26

申请号：US17107181

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien-Hsun Lee

IPC: H01L23/02 ,  H01L23/538 ,  H01L23/31 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

公开(公告)号：US20230386866A1

公开(公告)日：2023-11-30

申请号：US18447428

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/565 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/481 ,  H01L24/19 ,  H01L23/3128 ,  H01L2224/73267 ,  H01L2224/12105

Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect co

公开(公告)号：US11830797B2

公开(公告)日：2023-11-28

申请号：US17359782

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L25/16 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/16 ,  H01L28/40

Abstract: A package includes a first layer of molding material, a first metallization layer on the first layer of molding material, a second layer of molding material on the first metallization layer and the first layer of molding material, a second metallization layer on the second layer of molding material, through vias within the second layer of molding material, the through vias extending from the first metallization layer to the second metallization layer, integrated passive devices within the second layer of molding material, a redistribution structure electrically on the second metallization layer and the second layer of molding material, the redistribution structure connected to the through vias and the integrated passive devices, and at least one semiconductor device on the redistribution structure, the at least one semiconductor device connected to the redistribution structure.

公开(公告)号：US20230377907A1

公开(公告)日：2023-11-23

申请号：US18150557

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L21/56 ,  G02B6/12 ,  H01L21/683 ,  H01L23/538

CPC classification number: H01L21/565 ,  G02B6/12004 ,  H01L21/6835 ,  H01L23/5389 ,  G02B2006/12147 ,  H01L2221/68345

Abstract: A method of forming a semiconductor package includes: bonding a first wafer to a second wafer, where the first wafer includes a plurality of electronic dies, and the second wafer includes a plurality of photonic dies; after bonding the first wafer, forming trenches in the second wafer between adjacent ones of the plurality of photonic dies; filling the trenches with an optical glue; and dicing the first wafer and the second wafer to form a plurality of photonic packages, where a photonic package of the plurality of photonic packages includes an electronic die, a photonic die bonded to the electronic die, and the optical glue, where the optical glue extends along a sidewall of the photonic package.

公开(公告)号：US20230369249A1

公开(公告)日：2023-11-16

申请号：US18359684

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L24/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L21/4857 ,  H01L2924/3512 ,  H01L2224/16227 ,  H01L2924/35121 ,  H01L2924/3511

Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

公开(公告)号：US20230326850A1

公开(公告)日：2023-10-12

申请号：US18334843

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chien-Hsun Chen

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L25/16 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/97 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/02373

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

公开(公告)号：US20230091737A1

公开(公告)日：2023-03-23

申请号：US17994841

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US11605621B2

公开(公告)日：2023-03-14

申请号：US17121361

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jiun Yi Wu ,  Hsing-Kuo Hsia

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L31/18 ,  H01L31/02 ,  H01L23/66

Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

公开(公告)号：US20230062146A1

公开(公告)日：2023-03-02

申请号：US17458854

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

公开(公告)号：US20220302067A1

公开(公告)日：2022-09-22

申请号：US17832949

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.