公开(公告)号：US20240379535A1

公开(公告)日：2024-11-14

申请号：US18779329

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US11315862B2

公开(公告)日：2022-04-26

申请号：US16916046

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lin Ho ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Chi-Yang Yu ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

公开(公告)号：US20210098354A1

公开(公告)日：2021-04-01

申请号：US16796905

申请日：2020-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Jiun-Yi Wu ,  Yu-Min Liang

IPC: H01L23/498 ,  H01L23/00

Abstract: A package structure including a first circuit board structure, a redistribution layer structure, bonding elements, and a semiconductor package is provided. The redistribution layer structure is disposed over and electrically connected to the first circuit board structure. The bonding elements are disposed between and electrically connected to the redistribution layer structure and the first circuit board structure. Each of the bonding elements has a core portion and a shell portion surrounding the core portion. A stiffness of the core portion is higher than a stiffness of the shell portion. A semiconductor package is disposed over and electrically connected to the redistribution layer structure.

公开(公告)号：US20200279790A1

公开(公告)日：2020-09-03

申请号：US16874621

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Wen-Lin Chen

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

公开(公告)号：US11705378B2

公开(公告)日：2023-07-18

申请号：US16933910

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Jiun-Yi Wu ,  Hsin-Yu Pan ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/31 ,  H01L23/40 ,  H01L23/538

CPC classification number: H01L23/3135 ,  H01L23/4012 ,  H01L23/5383

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

公开(公告)号：US20200176405A1

公开(公告)日：2020-06-04

申请号：US16521601

申请日：2019-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Yi Wu ,  Chen-Hua Yu ,  Yu-Min Liang

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a circuit board structure, a first redistribution layer structure, a plurality of first bonding elements, a package structure and a plurality of second bonding elements. The first redistribution layer structure is disposed over and electrically connected to the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the circuit board structure. The package structure is disposed over and electrically connected to the first redistribution layer structure. The second bonding elements are disposed between and electrically connected to the first redistribution layer structure and the package structure.

公开(公告)号：US20190096816A1

公开(公告)日：2019-03-28

申请号：US15719493

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lin Ho ,  Chin-Liang Chen ,  Chi-Yang Yu ,  Yu-Min Liang

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.

公开(公告)号：US20240363366A1

公开(公告)日：2024-10-31

申请号：US18771181

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20230307375A1

公开(公告)日：2023-09-28

申请号：US18151583

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Tsung-Ding Wang ,  Jung Wei Cheng ,  Yu-Min Liang ,  Chien-Hsun Lee ,  Shang-Yun Hou ,  Wei-Yu Chen ,  Collin Jordon Fleshman ,  Kuo-Lung Pan ,  Shu-Rong Chun ,  Sheng-Chi Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H10B80/00 ,  H01L25/18 ,  H01L21/561 ,  H01L23/481 ,  H01L23/562 ,  H01L2224/16227 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29386 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0503 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/19 ,  H01L2224/211

Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

公开(公告)号：US11355461B2

公开(公告)日：2022-06-07

申请号：US16914478

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/683

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.