公开(公告)号：US20120193729A1

公开(公告)日：2012-08-02

申请号：US13017809

申请日：2011-01-31

申请人： TAKASHI ANDO ,  Christian Lavoie ,  Vijay Narayanan

发明人： TAKASHI ANDO ,  Christian Lavoie ,  Vijay Narayanan

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66606 ,  H01L29/66628 ,  H01L29/7848

摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

摘要翻译： 用于器件制造的器件和方法包括用牺牲材料形成栅极结构。 硅化区域形成在与栅极结构相邻的源极/漏极区域上，或者形成在源极/漏极区域内的沟槽触点的底部。 对源极/漏极区域或硅化物区域进行处理，以建立对后续热处理的阻力，并调整肖特基势垒高度，从而降低接触电阻。 金属触点形成为与硅化物区域接触。 去除牺牲材料并用替换导体代替。

公开(公告)号：US20110309455A1

公开(公告)日：2011-12-22

申请号：US12816605

申请日：2010-06-16

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US08680629B2

公开(公告)日：2014-03-25

申请号：US12477536

申请日：2009-06-03

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/71

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/513 ,  H01L29/78

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.

公开(公告)号：US08592296B2

公开(公告)日：2013-11-26

申请号：US12816605

申请日：2010-06-16

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L21/3205

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US20120326245A1

公开(公告)日：2012-12-27

申请号：US13605267

申请日：2012-09-06

申请人： Takashi Ando ,  Vijay Narayanan

发明人： Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L29/78

CPC分类号： H01L29/4966 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/66606 ,  H01L29/7833

摘要： A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer.

摘要翻译： 形成晶体管器件的方法包括在半导体衬底上形成对应于衬底中形成的掺杂源极和漏极区域之间的界面层; 在界面层上形成高介电常数（高k）层，高k层的介电常数大于约7.5; 在高k层上形成掺杂金属层; 进行热处理以使掺杂的金属层清除从界面层扩散的氧原子，使得界面层的最终厚度小于约5埃（）; 以及在高k电介质层上形成金属栅极材料。

公开(公告)号：US20120280288A1

公开(公告)日：2012-11-08

申请号：US13100371

申请日：2011-05-04

申请人： Takashi Ando ,  Vijay Narayanan

发明人： Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/66606 ,  H01L29/7833

摘要： A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer.

公开(公告)号：US20120276720A1

公开(公告)日：2012-11-01

申请号：US13547792

申请日：2012-07-12

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/20

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

摘要翻译： 用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。 栅极堆叠包括形成在半导体衬底上的锗（Ge）材料层，形成在Ge材料层上的扩散阻挡层，在扩散阻挡层上形成的具有大于约3.9的高介电常数的高k电介质，以及 形成在高k电介质层上方的导电电极层。

公开(公告)号：US20120139053A1

公开(公告)日：2012-06-07

申请号：US12960586

申请日：2010-12-06

申请人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7848

摘要： A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

摘要翻译： 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。

公开(公告)号：US08796784B2

公开(公告)日：2014-08-05

申请号：US13604036

申请日：2012-09-05

申请人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

发明人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

IPC分类号： H01L21/02

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66606 ,  H01L29/66628 ,  H01L29/7848

摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

摘要翻译： 用于器件制造的器件和方法包括用牺牲材料形成栅极结构。 硅化区域形成在与栅极结构相邻的源极/漏极区域上，或者形成在源极/漏极区域内的沟槽触点的底部。 对源极/漏极区域或硅化物区域进行处理，以建立对后续热处理的阻力，并调整肖特基势垒高度，从而降低接触电阻。 金属触点形成为与硅化物区域接触。 去除牺牲材料并用替换导体代替。

公开(公告)号：US08785322B2

公开(公告)日：2014-07-22

申请号：US13017809

申请日：2011-01-31

申请人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

发明人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

IPC分类号： H01L21/4763 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66606 ,  H01L29/66628 ,  H01L29/7848

摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.