公开(公告)号：US11064120B2

公开(公告)日：2021-07-13

申请号：US16736940

申请日：2020-01-08

申请人： Takashi Ando

发明人： Takashi Ando

IPC分类号： H04N5/232 ,  H04N5/225 ,  G03B5/00

摘要： An imaging-element inclination adjustment mechanism including at least one adjustment member attached to an imaging-element unit in a manner that a position of the adjustment member is adjustable relative to the imaging-element unit, the imaging-element unit holding an imaging element; at least one support member secured to a housing; and at least one securing member engaged with the adjustment member and attached to the support member. The position of the adjustment member is adjusted relative to the imaging-element unit to adjust a position of the imaging-element unit relative to the support member. The support member supports the imaging-element unit via the adjustment member at each of at least three positions.

公开(公告)号：US08853751B2

公开(公告)日：2014-10-07

申请号：US13614962

申请日：2012-09-13

申请人： Takashi Ando ,  Martin M. Frank ,  Vijay Narayanan

发明人： Takashi Ando ,  Martin M. Frank ,  Vijay Narayanan

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/82345 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66522

摘要： A semiconductor structure includes a high mobility semiconductor, an interfacial oxide layer, a high dielectric constant (high-k) layer, a stack, a gate electrode, and a gate dielectric. The stack comprises a lower metal layer, a scavenging metal layer comprising a scavenging metal, and an upper metal layer formed on the scavenging metal layer. A Gibbs free energy change of a chemical reaction, in which an atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer combines with a metal oxide material comprising the scavenging metal and oxygen to form the scavenging metal in elemental form and oxide of the atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer, is positive.

摘要翻译： 半导体结构包括高迁移率半导体，界面氧化物层，高介电常数（高k）层，堆叠，栅极电极和栅极电介质。 堆叠包括下金属层，包含清除金属的清除金属层和形成在扫气金属层上的上金属层。 化学反应的吉布斯自由能变化，其中构成直接与界面氧化物层接触的高迁移率半导体层的原子与包含清除金属和氧的金属氧化物材料结合，以形成元素形式的清除金属和氧化物 构成与界面氧化物层直接接触的高迁移率半导体层的原子为正。

公开(公告)号：US08796784B2

公开(公告)日：2014-08-05

申请号：US13604036

申请日：2012-09-05

申请人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

发明人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

IPC分类号： H01L21/02

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66606 ,  H01L29/66628 ,  H01L29/7848

摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

摘要翻译： 用于器件制造的器件和方法包括用牺牲材料形成栅极结构。 硅化区域形成在与栅极结构相邻的源极/漏极区域上，或者形成在源极/漏极区域内的沟槽触点的底部。 对源极/漏极区域或硅化物区域进行处理，以建立对后续热处理的阻力，并调整肖特基势垒高度，从而降低接触电阻。 金属触点形成为与硅化物区域接触。 去除牺牲材料并用替换导体代替。

公开(公告)号：US08785322B2

公开(公告)日：2014-07-22

申请号：US13017809

申请日：2011-01-31

申请人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

发明人： Takashi Ando ,  Christian Lavoie ,  Vijay Narayanan

IPC分类号： H01L21/4763 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66606 ,  H01L29/66628 ,  H01L29/7848

摘要： Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

公开(公告)号：US08736043B2

公开(公告)日：2014-05-27

申请号：US13544339

申请日：2012-07-09

申请人： Akitoyo Konno ,  Katsunori Azuma ,  Takashi Ando

发明人： Akitoyo Konno ,  Katsunori Azuma ,  Takashi Ando

IPC分类号： H05K1/03 ,  H01L23/49 ,  H01L25/07 ,  H01L29/417

CPC分类号： H01L23/49 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/49 ,  H01L25/072 ,  H01L29/417 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2924/00014

摘要： A power semiconductor device is provided in which reliability can be improved when the parallel number of semiconductor devices increases. When a bonding face on collector electrode is on an upper side, and a bonding face on emitter electrode is on a lower side, a collector electrode joint region as a joint region between a collector trace and a collector electrode on a chip mounted substrate and an emitter electrode joint region as a joint region between an emitter trace and an emitter electrode are located at a same position in an up-and-down direction and are adjacent in a right-and-left direction at an interval of 2 mm or more and 4 mm or less.

摘要翻译： 提供一种功率半导体器件，其中当半导体器件的平行数量增加时可以提高可靠性。 当集电极上的接合面在上侧，发射电极的接合面位于下侧时，集电极接合区域作为芯片安装基板上的集电体迹线与集电极之间的接合区域， 作为发射极和发射极之间的接合区域的发射极电极接合区域位于上下方向的相同位置，并且在左右方向上以2mm以上的间隔相邻， 4毫米或更小。

公开(公告)号：US08716118B2

公开(公告)日：2014-05-06

申请号：US13345295

申请日：2012-01-06

申请人： Takashi Ando ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

摘要： A transistor includes a semiconductor layer and a gate structure located on the semiconductor layer. The gate structure includes a first dielectric layer. The first dielectric layer includes a doped region and an undoped region below the doped region. A second dielectric layer is located on the first dielectric layer, and a first metal nitride layer is located on the second dielectric layer. The doped region of the first dielectric layer comprises dopants from the second dielectric layer. Source and drain regions in the semiconductor layer are located on opposite sides of the gate structure.

摘要翻译： 晶体管包括位于半导体层上的半导体层和栅极结构。 栅极结构包括第一介电层。 第一介电层包括掺杂区域和掺杂区域下面的未掺杂区域。 第二电介质层位于第一电介质层上，第一金属氮化物层位于第二电介质层上。 第一介电层的掺杂区域包括来自第二介电层的掺杂剂。 半导体层中的源极和漏极区位于栅极结构的相对侧上。

公开(公告)号：US08659077B1

公开(公告)日：2014-02-25

申请号：US13615343

申请日：2012-09-13

申请人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

发明人： Takashi Ando ,  Aritra Dasgupta ,  Unoh Kwon ,  Sean M. Polvino

IPC分类号： H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

摘要： Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

摘要翻译： 实施例涉及场效应晶体管（FET）替换门装置。 该装置包括一个通道结构，该通道结构包括限定沟槽的底座和侧壁。 在沟槽的底壁和侧壁上形成高介电常数（高k）层。 高k层具有与沟槽形状一致的上表面。 第一层形成在高k层上并符合沟槽的形状。 第一层包括无铝的金属氮化物。 在第一层上形成第二层并符合沟槽的形状。 第二层包括铝和至少一种其他金属。 第三层形成在第二层上并符合沟槽的形状。 第三层包括无铝金属氮化物。

公开(公告)号：US08507383B2

公开(公告)日：2013-08-13

申请号：US13012879

申请日：2011-01-25

申请人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

发明人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

IPC分类号： H01L21/302 ,  C03C15/00 ,  C23F1/00

CPC分类号： H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

摘要： Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

摘要翻译： 用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。 采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

公开(公告)号：US08486748B2

公开(公告)日：2013-07-16

申请号：US13027638

申请日：2011-02-15

申请人： Harumi Ikeda ,  Susumu Hiyama ,  Takashi Ando ,  Kiyotaka Tabuchi ,  Tetsuji Yamaguchi ,  Yuko Ohgishi

发明人： Harumi Ikeda ,  Susumu Hiyama ,  Takashi Ando ,  Kiyotaka Tabuchi ,  Tetsuji Yamaguchi ,  Yuko Ohgishi

IPC分类号： H01L21/00 ,  H01L27/00

CPC分类号： H01L27/14636 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14818 ,  H01L27/14868

摘要： A solid-state imaging device having a light-receiving section that photoelectrically converts incident light includes an insulating film formed on a light-receiving surface of the light-receiving section and a film and having negative fixed charges formed on the insulating film. A hole accumulation layer is formed on a light-receiving surface side of the light-receiving section. A peripheral circuit section in which peripheral circuits are formed is provided on a side of the light-receiving section. The insulating film is formed between a surface of the peripheral circuit section and the film having negative fixed charges such that a distance from the surface of the peripheral circuit section to the film having negative fixed charges is larger than a distance from a surface of the light-receiving section to the film having negative fixed charges.

摘要翻译： 具有光电转换入射光的受光部的固体摄像装置具备形成在受光部的受光面上的绝缘膜和形成在绝缘膜上的负固定电荷的膜。 在光接收部的受光面侧形成有空穴积聚层。 形成有外围电路的外围电路部分设置在光接收部分的一侧。 绝缘膜形成在外围电路部分的表面和具有负固定电荷的膜之间，使得从外围电路部分的表面到具有负固定电荷的膜的距离大于距离光的表面的距离 接收部分电影有负固定费用。

公开(公告)号：US08404530B2

公开(公告)日：2013-03-26

申请号：US13177692

申请日：2011-07-07

申请人： Takashi Ando ,  Vijay Narayanan

发明人： Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/338

CPC分类号： H01L21/28088 ,  H01L21/28176 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

摘要： A disposable gate structure and a gate spacer are formed on a semiconductor substrate. A disposable gate material portion is removed and a high dielectric constant (high-k) gate dielectric layer and a metal nitride layer are formed in a gate cavity and over a planarization dielectric layer. The exposed surface portion of the metal nitride layer is converted into a metal oxynitride by a surface oxidation process that employs exposure to ozonated water or an oxidant-including solution. A conductive gate fill material is deposited in the gate cavity and planarized to provide a metal gate structure. Oxygen in the metal oxynitride diffuses, during a subsequent anneal process, into a high-k gate dielectric underneath to lower and stabilize the work function of the metal gate without significant change in the effective oxide thickness (EOT) of the high-k gate dielectric.

摘要翻译： 在半导体衬底上形成一次性栅极结构和栅极间隔物。 去除一次性栅极材料部分，并且在栅极腔中和平坦化介电层上形成高介电常数（高k）栅极电介质层和金属氮化物层。 金属氮化物层的暴露表面部分通过使用暴露于臭氧化水或含氧化剂的溶液的表面氧化工艺转化为金属氮氧化物。 导电栅极填充材料沉积在栅极腔中并被平坦化以提供金属栅极结构。 金属氧氮化物中的氧在随后的退火过程中扩散到下面的高k栅极电介质中，以降低和稳定金属栅极的功函数，而不会在高k栅极电介质的有效氧化物厚度（EOT）上显着变化 。