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73 条记录 (耗时 0.025 秒)

    Semiconductor device having dummy patterns for metal CMP
    63.
    发明授权
    Semiconductor device having dummy patterns for metal CMP 失效
    具有用于金属CMP的虚设图案的半导体器件

    公开(公告)号：US06784548B2

    公开(公告)日：2004-08-31

    申请号：US10309272

    申请日：2002-12-04

    申请人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

    发明人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

    IPC分类号： H01L2348

    CPC分类号： H01L27/08 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/823437 ,  H01L23/5227 ,  H01L23/528 ,  H01L29/42372 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

    摘要翻译： 栅电极具有例如约10μm的较长栅极长度。 在夹在所提供的第一层金属之间的栅电极正上方的区域是具有第一方向的宽度并且沿与栅极长度方向（电流方向）垂直的第二方向延伸的金属虚设图案。 此外，第二方向上的金属虚设图案的几何中心等于栅电极在第二方向上的几何中心。 这保持了从栅电极观察时的金属虚设图形的对称性。 这种结构可以使多种元素的特性劣化，同时保持金属CMP的基本效果。

    A/D converter having folded arrangement of voltage comparator
    64.
    发明授权
    A/D converter having folded arrangement of voltage comparator 失效
    A / D转换器具有电压比较器的折叠布置

    公开(公告)号：US5554989A

    公开(公告)日：1996-09-10

    申请号：US241422

    申请日：1994-05-11

    申请人： Toshio Kumamoto ,  Takahiro Miki

    发明人： Toshio Kumamoto ,  Takahiro Miki

    IPC分类号： H03M1/36 ,  H03M1/06

    CPC分类号： H03M1/0682 ,  H03M1/368

    摘要： Voltage comparators C.sub.1 -C.sub.N for comparing a first differential reference voltage obtained by dividing a first reference voltage V.sub.RT and a second reference voltage V.sub.RB by ladder resistors r.sub.1 -r.sub.N+1 and a second differential reference input voltage formed by a third voltage V.sub.i and a fourth voltage V.sub.i are arranged in first to N/2 and (N/2+1)-th to N-th voltage comparator rows in a folded manner and wiring area can be reduced as a result.

    摘要翻译： 电压比较器C1-CN，用于比较通过用梯形电阻器r1-rN + 1划分第一参考电压VRT和第二参考电压VRB获得的第一差分参考电压和由第三电压Vi和第四电压形成的第二差分参考输入电压 电压+ E，ovs Vi + EE以折叠方式排列在第一至N / 2和（N / 2 + 1）至第N电压比较器行中，结果可以减少配线区域。

    Differential amplifier, comparator and high-speed A/D converter using the same
    65.
    发明授权
    Differential amplifier, comparator and high-speed A/D converter using the same 失效
    差分放大器，比较器和高速A / D转换器使用相同

    公开(公告)号：US5396131A

    公开(公告)日：1995-03-07

    申请号：US988599

    申请日：1992-12-10

    申请人： Takahiro Miki ,  Toshio Kumamoto

    发明人： Takahiro Miki ,  Toshio Kumamoto

    IPC分类号： H03F3/45 ,  H03K3/2885 ,  H03K5/08 ,  H03K5/24 ,  H03M1/14 ,  H03M1/34 ,  H03M1/36

    CPC分类号： H03K3/2885 ,  H03K5/2418 ,  H03K5/2427 ,  H03M1/362

    摘要： Disclosed is a high-speed A/D converter (15) including an improved differential amplifier circuit. Each comparator (61) provided in the A/D converter directly receives a complementary or differential analog input voltage to be converted. A differential amplifier circuit provided in each comparator compares an applied analog input voltage difference and an applied reference voltage difference. A binary signal indicative of a comparison result is applied to an encoder (4) through a binarization circuit. An analog input voltage which is not to be converted is directly applied to the comparator, that is, to the differential amplifier circuit through none of resistor elements and components, whereby conversion time delay is prevented.

    摘要翻译： 公开了一种包括改进的差分放大器电路的高速A / D转换器（15）。 设置在A / D转换器中的每个比较器（61）直接接收待转换的互补或差分模拟输入电压。 在每个比较器中提供的差分放大器电路比较所施加的模拟输入电压差和施加的参考电压差。 指示比较结果的二进制信号通过二值化电路施加到编码器（4）。 将不转换的模拟输入电压直接施加到比较器，即不通过电阻元件和元件对差分放大器电路施加，从而防止转换时间延迟。

    Controlled threshold type electric device and comparator employing the same
    66.
    发明授权
    Controlled threshold type electric device and comparator employing the same 失效
    控制型THRESHOLD型电气设备和使用该电气设备的比较器

    公开(公告)号：US5099146A

    公开(公告)日：1992-03-24

    申请号：US539828

    申请日：1990-06-18

    申请人： Takahiro Miki ,  Shiro Hosotani ,  Toshio Kumamoto

    发明人： Takahiro Miki ,  Shiro Hosotani ,  Toshio Kumamoto

    IPC分类号： H01L29/78 ,  H03K3/22 ,  H03K5/08 ,  H03K17/30 ,  H03K17/687 ,  H03M1/36

    CPC分类号： H03K5/086 ,  H01L2924/0002

    摘要： In a controlled threshold type electric device having first and second transistors and a differential amplifier which receives a reference input voltage, a voltage corresponding to the threshold voltage of the first transistor itself is applied to the differential amplifier as a feedback input voltage. The differential amplifier compares the received feed back input voltage with the reference input voltage and applies a control voltage to the backgate of the first transistor so that the threshold value of the first transistor converges to a desired value. This control voltage is also applied to the backgate of the second transistor so that the threshold voltage of the second transistor also converges to a desired value. Since the voltage corresponding to the threshold value of the first transistor is applied to the differential amplifier, an accurate feed back control is made. Further, since the differential amplifier can be manufactured through the MOS standard process, the manufacturing cost can be reduced.

    摘要翻译： 在具有第一和第二晶体管的受控阈值型电器件和接收参考输入电压的差分放大器中，将与第一晶体管本身的阈值电压相对应的电压作为反馈输入电压施加到差分放大器。 差分放大器将接收的反馈输入电压与参考输入电压进行比较，并将控制电压施加到第一晶体管的背栅极，使得第一晶体管的阈值收敛到期望值。 该控制电压也被施加到第二晶体管的背栅，使得第二晶体管的阈值电压也收敛到期望值。 由于将对应于第一晶体管的阈值的电压施加到差分放大器，因此进行精确的反馈控制。 此外，由于可以通过MOS标准工艺制造差分放大器，所以可以降低制造成本。

    Sample hold circuit having a switch
    67.
    发明授权
    Sample hold circuit having a switch 失效
    具有开关的采样保持电路

    公开(公告)号：US06232804B1

    公开(公告)日：2001-05-15

    申请号：US09413751

    申请日：1999-10-06

    申请人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

    发明人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

    IPC分类号： G11C2702

    CPC分类号： G11C27/026

    摘要： In a sample hold circuit (6, 50, 60) capable of relaxing a dependency of a voltage of an analogue input signal on an ON resistance of a switch (2). In the sample hold circuit (6, 50, 60), plural reference voltages VrefN are supplied, and unit switches (11e) forming the switch (2) are selectively activated (an ON state) based on a comparison results (whether or not the voltage of the analogue input signal is greater than each reference voltage) from plural comparison circuits (13e) whose operations are performed based on the voltage of the analogue input signal (1).

    摘要翻译： 在能够放松模拟输入信号的电压对开关（2）的导通电阻的依赖性的采样保持电路（6,50,60）中。 在采样保持电路（6,50,60）中，提供多个参考电压VrefN，并且基于比较结果（形成开关（2））的单元开关（11e）是否被选择性地激活（ON状态） 根据模拟输入信号（1）的电压执行其操作的多个比较电路（13e），模拟输入信号的电压大于每个参考电压）。

    Analog-to-digital converter
    68.
    发明授权
    Analog-to-digital converter 失效
    模数转换器

    公开(公告)号：US5731776A

    公开(公告)日：1998-03-24

    申请号：US714423

    申请日：1996-09-16

    申请人： Toshio Kumamoto ,  Osamu Matsumoto

    发明人： Toshio Kumamoto ,  Osamu Matsumoto

    IPC分类号： H03M1/14 ,  H03M1/36

    CPC分类号： H03M1/362

    摘要： A ladder resistance (1) consisting of resistance elements (r1, r2, . . . , r8) connected in series with intermediate taps (T1, T2, . . . , T7) interposed is so arranged as to be folded back at its midpoint. Pairs of differential comparators (C1 and C7, C2 and C6, . . . ) which are connected to common intermediate taps are each disposed adjacently so as to be nearest to the intermediate tap to be connected thereto. Accordingly, wires connecting the differential comparators (C1, C2, . . . , C7) to the intermediate taps (T1, T2, . . . , T7) become shorter and an area of a semiconductor chip needed for arranging the wires can be reduced. Thus, reduction in area of the semiconductor chip needed for providing the device therein is achieved.

    摘要翻译： 插入与中间抽头（T1，T2，...，T7）串联连接的电阻元件（r1，r2，...，r8）组成的梯形电阻（1）被布置为在其中点 。 连接到公共中间抽头的差分比较器（C1和C7，C2和C6，...）的对相邻设置成最靠近要与其连接的中间抽头。 因此，将差分比较器（C1，C2，... C7）连接到中间抽头（T1，T2，...，T7）的电线变短，并且可以减少布线所需的半导体芯片的面积 。 因此，实现了在其中提供设备所需的半导体芯片的面积减小。

    Transistor circuit
    69.
    发明授权
    Transistor circuit 失效
    晶体管电路

    公开(公告)号：US5469047A

    公开(公告)日：1995-11-21

    申请号：US311433

    申请日：1994-09-26

    申请人： Toshio Kumamoto ,  Takahiro Miki ,  Hiroyuki Kouno

    发明人： Toshio Kumamoto ,  Takahiro Miki ,  Hiroyuki Kouno

    IPC分类号： G05F3/16 ,  G05F3/20

    CPC分类号： G05F3/20

    摘要： In order to obtain a constant current circuit which has an excellent constant current property and requires no plural bias circuits, a base of an NPN bipolar transistor (5) and a gate of an N-channel MOS transistor (6) are connected to a first terminal (1) in common. A collector of the transistor (5) is connected to a second terminal (2) and a source of a transistor (6) is connected to a third terminal respectively, while a voltage source (59) is connected between the first and third terminals. An emitter of the transistor (5) is connected with a drain of the transistor (6). Identical bias voltages are supplied to the base and the gate, while a gate-to-drain voltage of the transistor (6) is equal to a base-to-emitter voltage of the transistor (5). Thus, the transistor (6) operates in a pentode region, to serve as a constant current load for the transistor (5).

    摘要翻译： 为了获得具有优异的恒定电流特性并且不需要多个偏置电路的恒流电路，NPN双极晶体管（5）的基极和N沟道MOS晶体管（6）的栅极连接到第一 终端（1）共同点。 晶体管（5）的集电极连接到第二端子（2），并且晶体管（6）的源极分别连接到第三端子，而电压源（59）连接在第一和第三端子之间。 晶体管（5）的发射极与晶体管（6）的漏极连接。 相同的偏置电压被提供给基极和栅极，而晶体管（6）的栅极 - 漏极电压等于晶体管（5）的基极 - 发射极电压。 因此，晶体管（6）工作在五极管区域，用作晶体管（5）的恒定电流负载。

    Sample hold circuit, buffer circuit and sample hold apparatus using these circuits
    70.
    发明授权
    Sample hold circuit, buffer circuit and sample hold apparatus using these circuits 失效
    使用这些电路的采样保持电路，缓冲电路和采样保持装置

    公开(公告)号：US5341037A

    公开(公告)日：1994-08-23

    申请号：US886904

    申请日：1992-05-22

    申请人： Takahiro Miki ,  Toshio Kumamoto

    发明人： Takahiro Miki ,  Toshio Kumamoto

    IPC分类号： G11C27/02 ,  H03K5/159

    CPC分类号： G11C27/026 ,  G11C27/024

    摘要： Positive and negative output ends of a differential circuit in a sample hold circuit are connected to capacitors through switch circuits. Further, collectors of two input transistors of a buffer circuit connected to the sample hold circuit are driven by a collector driving differential circuit, so as to make the collector.multidot.base voltages of two input transistors same to each other. Consequently, a stable sample hold circuit having an arbitrary gain can be provided. In addition, drifts of outputs from two capacitors in the sample hold circuit can be made equal to each other by the buffer circuit.

    摘要翻译： 采样保持电路中的差分电路的正和负输出端通过开关电路连接到电容器。 此外，连接到采样保持电路的缓冲电路的两个输入晶体管的集电极由集电极驱动差分电路驱动，以使两个输入晶体管的集电极基极彼此相同。 因此，可以提供具有任意增益的稳定的采样保持电路。 此外，可以通过缓冲电路将采样保持电路中的两个电容器的输出漂移相互相等。