-
公开(公告)号：US5821893A
公开(公告)日：1998-10-13
申请号：US740520
申请日：1996-10-30
申请人： Toshio Kumamoto , Osamu Matsumoto
发明人： Toshio Kumamoto , Osamu Matsumoto
CPC分类号： H03M1/0695 , H03M1/167
摘要： In a pipeline type A/D converter, a switch for sampling an analog potential signal has its other terminal in connection with an A/D converter, a D/A converter, a capacitor for subtraction. Even when frequency of the analog potential signal is raised such that input current is increased and a voltage drop is increased at the switch, there will be no error in the result of subtraction like in the conventional example where analog potential signal was directly input to A/D converter. Accordingly, a pipeline type A/D converter with low power dissipation and satisfactory frequency characteristics is obtained.
摘要翻译： 在流水线型A / D转换器中，用于对模拟电位信号采样的开关具有与A / D转换器，D / A转换器，用于减法的电容器相连的另一端。 即使在模拟电位信号的频率升高使得输入电流增加并且在开关处电压降增加的情况下，与在将模拟电位信号直接输入到A的常规示例中一样，减法结果将不会有误差 / D转换器。 因此，获得具有低功耗和令人满意的频率特性的流水线型A / D转换器。
-
2.发明授权Analog/digital converter and voltage comparator capable of fast producing of output offset voltage 失效模拟/数字转换器和电压比较器能够快速产生输出失调电压
公开(公告)号：US5966088A
公开(公告)日：1999-10-12
申请号：US982279
申请日：1997-12-01
申请人： Osamu Matsumoto , Toshio Kumamoto
发明人： Osamu Matsumoto , Toshio Kumamoto
CPC分类号： H03M1/1023 , H03M1/168
摘要： An A/D converter includes a sample-hold circuit, A/D converting stages connected in series to the sample-hold circuit, and an encoder/latch circuit which adds 3-bit digital signals issued from the A/D converting stages to each other for outputting a signal of 9 bits. The sample-hold circuit and the A/D converting stages each include a differential amplifier. Differential outputs of each differential amplifier are short-circuited for a predetermined initial period in each sampling period.
摘要翻译： A / D转换器包括采样保持电路，与采样保持电路串联连接的A / D转换级，以及编码器/锁存电路，其将从A / D转换级发出的3位数字信号加到每个 另一个用于输出9位的信号。 采样保持电路和A / D转换级各自包括差分放大器。 在每个采样周期中，每个差分放大器的差分输出在预定的初始周期短路。
-
公开(公告)号：US5696511A
公开(公告)日：1997-12-09
申请号：US738585
申请日：1996-10-29
申请人： Osamu Matsumoto , Toshio Kumamoto
发明人： Osamu Matsumoto , Toshio Kumamoto
CPC分类号： H03M1/0695 , H03M1/167
摘要： In a pipeline type A/D converter, a sample/hold.cndot.subtracter circuit of an A/D converter block of a first stage samples an analog voltage and outputs an offset voltage at a first phase, and subtracts an output voltage of an A/D converter from the sampled analog voltage in a second phase. An A/D converter of an A/D converter block of a succeeding stage subtracts the output voltage of the sample/hold.cndot.subtracter circuit of the first phase from the output voltage of the sample hold.cndot.subtracter circuit of the second phase, and converts the subtracted result into a digital code. The influence of an offset of a differential amplifier included in the sample/hold.cndot.subtracter circuit is removed so that A/D conversion of high accuracy is allowed.
摘要翻译： 在流水线型A / D转换器中，第一级的A / D转换器模块的采样/保持减法器电路对模拟电压进行采样，并在第一阶段输出偏移电压，并且减去A / D转换器从第二阶段的采样模拟电压。 后级的A / D转换器模块的A / D转换器从第二相的采样保持电路的输出电压中减去第一相的采样/保持电路的输出电压，并将其转换 减去结果成数字代码。 除去包含在采样/保持抑制电路中的差分放大器的偏移的影响，使得允许高精度的A / D转换。
-
公开(公告)号：US5625308A
公开(公告)日：1997-04-29
申请号：US557556
申请日：1995-11-14
申请人： Osamu Matsumoto , Takahiro Miki , Toshio Kumamoto
发明人： Osamu Matsumoto , Takahiro Miki , Toshio Kumamoto
IPC分类号： H03M1/34 , H03K3/0233 , H03K3/356 , H03K3/289
CPC分类号： H03K3/35606 , H03K3/356034 , H03K3/35613
摘要： A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.
摘要翻译： 一种高性能差分锁存电路，包括由用作恒流源的NMOS晶体管（27），PMOS晶体管（3,4）和NMOS晶体管（23,24）组成的差分放大器电路，由NMOS 晶体管（25,26）以及由NMOS晶体管（21,22,28）组成的用于交替操作差分放大功能和锁存功能的开关电路，用作恒流源的晶体管（27）具有直接连接的漏极端子 到晶体管（23,24）和直接连接到接地电压（2）的源极端子，由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。
-
公开(公告)号：US5731776A
公开(公告)日：1998-03-24
申请号：US714423
申请日：1996-09-16
申请人： Toshio Kumamoto , Osamu Matsumoto
发明人： Toshio Kumamoto , Osamu Matsumoto
CPC分类号： H03M1/362
摘要： A ladder resistance (1) consisting of resistance elements (r1, r2, . . . , r8) connected in series with intermediate taps (T1, T2, . . . , T7) interposed is so arranged as to be folded back at its midpoint. Pairs of differential comparators (C1 and C7, C2 and C6, . . . ) which are connected to common intermediate taps are each disposed adjacently so as to be nearest to the intermediate tap to be connected thereto. Accordingly, wires connecting the differential comparators (C1, C2, . . . , C7) to the intermediate taps (T1, T2, . . . , T7) become shorter and an area of a semiconductor chip needed for arranging the wires can be reduced. Thus, reduction in area of the semiconductor chip needed for providing the device therein is achieved.
摘要翻译： 插入与中间抽头（T1，T2，...，T7）串联连接的电阻元件（r1，r2，...，r8）组成的梯形电阻（1）被布置为在其中点 。 连接到公共中间抽头的差分比较器（C1和C7，C2和C6，...）的对相邻设置成最靠近要与其连接的中间抽头。 因此，将差分比较器（C1，C2，... C7）连接到中间抽头（T1，T2，...，T7）的电线变短，并且可以减少布线所需的半导体芯片的面积 。 因此，实现了在其中提供设备所需的半导体芯片的面积减小。
-
6.发明授权
公开(公告)号：US5629700A
公开(公告)日：1997-05-13
申请号：US552016
申请日：1995-11-02
申请人： Toshio Kumamoto , Osamu Matsumoto , Takahiro Miki , Masao Ito , Takashi Okuda
发明人： Toshio Kumamoto , Osamu Matsumoto , Takahiro Miki , Masao Ito , Takashi Okuda
CPC分类号： H03M1/002 , H03M1/0682 , H03M1/069 , H03M1/1215 , H03M1/167
摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.
摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。
-
公开(公告)号：US08223050B2
公开(公告)日：2012-07-17
申请号：US12911345
申请日：2010-10-25
IPC分类号： H03M1/20
摘要： In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.
摘要翻译： 在具有用于将模拟输入信号转换为数字信号的多个通道的Δ-ΣA / D转换器中，在每个通道中降低了空闲音调的不利影响。 Δ-ΣA / D转换器包括：量化并输出接收信号的第一量化器; 第一D / A转换器，其将第一量化器的输出信号转换为模拟信号，并输出转换的模拟信号; 第一操作单元，其输出表示第一模拟输入信号和第一D / A转换器的输出信号的差的信号; 第一积分器，其对第一运算单元的输出信号进行积分并输出积分信号; 产生第一抖动信号的第一抖动电路; 以及第二操作单元，其将第一抖动信号添加到第一积分器的输出信号，并将相加的信号输出到第一量化器。
-
公开(公告)号：US08188526B2
公开(公告)日：2012-05-29
申请号：US12958923
申请日：2010-12-02
申请人： Takashi Okuda , Toshio Kumamoto
发明人： Takashi Okuda , Toshio Kumamoto
CPC分类号： H01L23/585 , H01L27/0248 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.
摘要翻译： 本发明的目的是确保将模拟块中的预定半导体元件或预定半导体元件组与数字块产生的噪声保护起来。 根据本发明的半导体器件包括半导体衬底，作为形成数字电路的区域的数字块和形成模拟电路的区域的模拟块，通过将模拟电路的上表面 半导体基板和设置在半导体基板上的基板电位固定区域，以在平面图中包围模拟块中的预定半导体元件组，以及连接到基板电位固定区域并从外部接收预定电位的焊盘 部分。
-
公开(公告)号：US07915708B2
公开(公告)日：2011-03-29
申请号：US12485528
申请日：2009-06-16
申请人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。
-
公开(公告)号：US07868413B2
公开(公告)日：2011-01-11
申请号：US12267166
申请日：2008-11-07
申请人： Takashi Okuda , Toshio Kumamoto
发明人： Takashi Okuda , Toshio Kumamoto
IPC分类号： H01L21/762
CPC分类号： H01L23/585 , H01L27/0248 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.
摘要翻译： 本发明的目的是确保将模拟块中的预定半导体元件或预定半导体元件组与数字块产生的噪声保护起来。 根据本发明的半导体器件包括半导体衬底，作为形成数字电路的区域的数字块和形成模拟电路的区域的模拟块，通过将模拟电路的上表面 半导体基板和设置在半导体基板上的基板电位固定区域，以在平面图中包围模拟块中的预定半导体元件组，以及连接到基板电位固定区域并从外部接收预定电位的焊盘 部分。
-
-
-
-
-
-
-
-
-
搜索结果
73 条记录 (耗时 0.022 秒)
