公开(公告)号：US20130033928A1

公开(公告)日：2013-02-07

申请号：US13576913

申请日：2010-02-02

申请人： Takayuki Kawahara ,  Riichiro Takemura ,  Kazuo Ono ,  Nobuaki Kohinata

发明人： Takayuki Kawahara ,  Riichiro Takemura ,  Kazuo Ono ,  Nobuaki Kohinata

IPC分类号： G11C11/16

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693

摘要： Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.

摘要翻译： 由于非易失性RAM允许随机读取和写入操作，因此不需要擦除模式。 然而，从系统侧，由于其非易失性特性，期望具有擦除模式。 此外，擦除操作期望以低功耗高速进行。 因此，提供了包含具有磁阻元件的多个存储单元MC的存储单元阵列COA和DTA，将一系列数据写入存储单元阵列COA和DTA，并且在擦除时，进行擦除操作 通过将预定数据仅写入存储单元阵列COA来实现。

公开(公告)号：US08228724B2

公开(公告)日：2012-07-24

申请号：US13345231

申请日：2012-01-06

申请人： Riichiro Takemura ,  Kenzo Kurotsuchi ,  Takayuki Kawahara

发明人： Riichiro Takemura ,  Kenzo Kurotsuchi ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： H01L47/00 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

摘要翻译： 例如，一个存储单元被配置为使用两个存储单元晶体管和一个相变元件，通过将多个扩散层与位线平行地布置，在扩散层之间设置栅极以跨越位线，布置位 线接触和源触点交替地布置到针对每个扩散层的位线方向上的多个扩散层，以及在源极触点上提供相变元件。 此外，相位元件可以设置在位线触点上而不是源极触点。 通过这种方式，例如，可以实现存储单元晶体管的驱动性的提高和面积的减小。

公开(公告)号：US20110194361A1

公开(公告)日：2011-08-11

申请号：US13122732

申请日：2009-10-05

申请人： Takayuki Kawahara ,  Riichiro Takemura ,  Kazuo Ono

发明人： Takayuki Kawahara ,  Riichiro Takemura ,  Kazuo Ono

IPC分类号： G11C7/14 ,  G11C7/06

CPC分类号： G11C11/1675 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/228

摘要： An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.

摘要翻译： 实现能够在小面积中提供必要且足够的电流的阵列配置，并且实现适合于TMR元件的温度特性的参考单元配置。 在使用反转自旋转移切换的存储器中，多个程序驱动器沿着一个全局位线分开布置，并且一个读出放大器被提供给一个全局位线。 “1”和“0”被编程的参考单元由两个阵列和一个读出放大器共用。

公开(公告)号：US07732864B2

公开(公告)日：2010-06-08

申请号：US11492054

申请日：2006-07-25

申请人： Takayuki Kawahara ,  Masanao Yamaoka

发明人： Takayuki Kawahara ,  Masanao Yamaoka

IPC分类号： H01L23/62

CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

公开(公告)号：US20100061169A1

公开(公告)日：2010-03-11

申请号：US12620903

申请日：2009-11-18

申请人： Masanao YAMAOKA ,  Takayuki Kawahara

发明人： Masanao YAMAOKA ,  Takayuki Kawahara

IPC分类号： G11C7/00

CPC分类号： H03K19/0016 ,  G11C11/413

摘要： An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state.A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

摘要翻译： 本发明的目的是提供一种降低驱动电路的泄漏电流的技术，该驱动电路在处于其待机状态时必须保持电位（或信息）的驱动电路。 本发明的半导体集成电路器件包括用于驱动电路块的驱动电路。 该驱动电路由具有不同栅极氧化膜厚度的栅极的双栅极晶体管构成。 当电路块处于其待机状态时，具有较薄栅极氧化膜的双栅极晶体管的栅极截止，并且具有较厚栅极氧化膜的栅极导通。 这种布置允许减少电路块和驱动电路的漏电流，同时允许驱动电路传送或切断电路块的电力。

公开(公告)号：US07639525B2

公开(公告)日：2009-12-29

申请号：US11541542

申请日：2006-10-03

申请人： Masanao Yamaoka ,  Takayuki Kawahara

发明人： Masanao Yamaoka ,  Takayuki Kawahara

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C11/34 ,  G11C5/14

CPC分类号： G11C11/412

摘要： A semiconductor memory device for reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode is provided. The semiconductor memory device also prevents an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area, and ensures stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

摘要翻译： 一种半导体存储器件，用于降低使用按比例缩小晶体管的整个低功耗SRAM LSI电路的功耗，并且通过减少亚阈值漏电流和从该存储器单元流出的漏电流来增加对存储单元的读和写操作的稳定性 漏电极到基板电极。 半导体存储器件还防止了存储单元中的晶体管数量的增加，从而防止了单元面积的增加，并且确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作由 控制驱动晶体管的BOX层下的阱的电位。

公开(公告)号：US07492655B2

公开(公告)日：2009-02-17

申请号：US11737693

申请日：2007-04-19

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US07405588B2

公开(公告)日：2008-07-29

申请号：US10933272

申请日：2004-09-03

申请人： Takayuki Kawahara ,  Masayuki Miyazaki ,  Yasushi Goto ,  Natsuki Yokoyama ,  Takahiro Onai

发明人： Takayuki Kawahara ,  Masayuki Miyazaki ,  Yasushi Goto ,  Natsuki Yokoyama ,  Takahiro Onai

IPC分类号： H03K19/173

CPC分类号： G11C23/00 ,  H03K19/1776 ,  H03K19/1778

摘要： The present invention relates to an LSI in which functions can be changed, and realizes, particularly, a system LSI in which functions are changed by changing connections of the circuit by use of MEMS switches. A bistable MEMS switch which can maintain states, and exhibits optimal stitching property, i.e., the switch has a very small resistance of several Ω or less in an on-state, and has an infinite resistance in an off-state; is employed. An element in which functions can be changed during operation, is produced by utilizing a wiring layer of a CMOS semiconductor to form the MEMS switch. A semiconductor device exhibiting high-degree of freedom for changing functions, high-speed, and having small area, is realized.

摘要翻译： 本发明涉及可以改变功能的LSI，特别是实现通过使用MEMS开关改变电路的连接来改变功能的系统LSI。 可以保持状态并且表现出最佳缝合性能的双稳态MEMS开关，即开关在导通状态下具有几欧姆或更小的非常小的电阻，并且在断开状态下具有无限电阻; 被雇用。 通过使用CMOS半导体的布线层来形成功能可以在操作期间改变的元件来形成MEMS开关。 实现了具有高自由度，高速度，小面积化的高自由度的半导体装置。

公开(公告)号：US07338261B2

公开(公告)日：2008-03-04

申请号：US10797567

申请日：2004-03-11

申请人： Takayuki Kawahara ,  Hiromitsu Adachi ,  Shinichirou Wakou ,  Hideki Watanabe

发明人： Takayuki Kawahara ,  Hiromitsu Adachi ,  Shinichirou Wakou ,  Hideki Watanabe

IPC分类号： F04B9/14

CPC分类号： F04C29/005 ,  F04C18/0238 ,  F04C18/0269 ,  F04C23/001 ,  F04C23/008 ,  F04C29/0085 ,  F04C2240/45

摘要： A hybrid compressor includes a first compression mechanism, which is driven by a first drive source, and a second compression mechanism, which is driven by a second drive source, and a second radial axis of a second housing of the second compression mechanism is offset relative to a first radial axis of a first housing of the first compression mechanism, or a second diameter of the second housing of the second compression mechanism is less than a first diameter of the first housing of the first compression mechanism, or both. When a significant external force is applied to the front end of a vehicle containing the compressor, most of the external force may be absorbed by the first compression mechanism portion of the compressor, thereby reducing or avoiding damage to the second compression mechanism. In particular, when the second drive source is an incorporated electric motor, damage to the electric motor may be reduced or avoided.

摘要翻译： 混合式压缩机包括由第一驱动源驱动的第一压缩机构和由第二驱动源驱动的第二压缩机构，并且第二压缩机构的第二壳体的第二径向轴线偏移相对 到第一压缩机构的第一壳体的第一径向轴线，或者第二压缩机构的第二壳体的第二直径小于第一压缩机构的第一壳体的第一直径或两者。 当对包含压缩机的车辆的前端施加显着的外力时，大部分外力可以被压缩机的第一压缩机构部分吸收，从而减少或避免对第二压缩机构的损坏。 特别地，当第二驱动源是并入的电动机时，可以减少或避免对电动机的损坏。

公开(公告)号：US20070187736A1

公开(公告)日：2007-08-16

申请号：US11737693

申请日：2007-04-19

申请人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： H01L29/94

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。