公开(公告)号：US07233537B2

公开(公告)日：2007-06-19

申请号：US10260397

申请日：2002-10-01

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Takaharu Tsuji ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Takaharu Tsuji ,  Tsukasa Ooishi

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2207/2281

摘要： Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

摘要翻译： 正常存储单元和虚设单元连续地布置在存储器阵列中。 在数据读取操作中，第一和第二数据线分别连接到所选择的存储单元和虚拟单元，并且被提供有差分放大器的工作电流。 在第一和第二数据线的通过电流之间提供对应于从电压产生电路施加的第一和第二偏移控制电压之间的电压差的偏移，并且通过虚设单元的参考电流被设置为两种之间的水平 的电平对应于通过所选存储单元的数据读取电流的存储数据。

公开(公告)号：US20050128800A1

公开(公告)日：2005-06-16

申请号：US11045100

申请日：2005-01-31

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/56

CPC分类号： G11C7/1051 ,  G11C7/06 ,  G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

摘要： In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.

摘要翻译： 在读取操作中，来自电流供给晶体管的电流流过选定的存储单元和数据线。 此外，具有不破坏存储数据的等级的偏置磁场被施加到所选存储单元。 通过施加偏置磁场，所选择的存储单元的电阻根据存储数据电平在正或负方向上变化。 读出放大器放大所选存储单元的电阻变化前后的数据线上的电压差。 因此，通过仅访问所选择的存储器单元，从所选择的存储器单元读取数据。 此外，由于数据线和读出放大器通过电容器彼此绝缘，所以无论存储器单元的磁化特性如何，读出放大器都可以在最佳输入电压范围内工作。

公开(公告)号：US06885235B2

公开(公告)日：2005-04-26

申请号：US10095080

申请日：2002-03-12

申请人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

发明人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/06 ,  G05F3/04

CPC分类号： G11C5/147

摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

摘要翻译： 内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。 过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号 表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。 因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

公开(公告)号：US06868004B2

公开(公告)日：2005-03-15

申请号：US10384741

申请日：2003-03-11

申请人： Hideto Hidaka ,  Masatoshi Ishikawa ,  Tsukasa Ooishi

发明人： Hideto Hidaka ,  Masatoshi Ishikawa ,  Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/14

CPC分类号： G11C11/16

摘要： An access transistor ATR in an MTJ memory cell, which is one of transistors connected to a read current path, is constituted with a surface-channel, field-effect transistor. The surface-channel, field-effect transistor has a channel resistance lower than a channel-embedded, field-effect transistor, and can reduce an RC load in the read current path. Accordingly, data can be read with a high speed.

摘要翻译： 作为与读取电流路径连接的晶体管之一的MTJ存储单元中的存取晶体管ATR由表面沟道场效应晶体管构成。 表面沟道场效应晶体管的沟道电阻低于通道嵌入的场效应晶体管，并且可以减小读取电流路径中的RC负载。 因此，可以高速读取数据。

公开(公告)号：US20050024935A1

公开(公告)日：2005-02-03

申请号：US10932057

申请日：2004-09-02

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/15 ,  G11C11/16

摘要： During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

摘要翻译： 在数据读取期间，根据行和列选择操作，激活感测使能信号以在形成包括数据线的当前路径和所选择的存储器单元之前开始数据线的充电。 早期完成数据线的充电，从而可以将开始数据读取所需的时间减少到数据线之间的通过电流差达到对应于所选存储单元的存储数据的电平的状态， 并且可以快速执行数据读取。

公开(公告)号：US06545926B2

公开(公告)日：2003-04-08

申请号：US09197566

申请日：1998-11-23

申请人： Tsukasa Ooishi ,  Hiroki Shimano ,  Hideto Hidaka ,  Shigeki Tomishima

发明人： Tsukasa Ooishi ,  Hiroki Shimano ,  Hideto Hidaka ,  Shigeki Tomishima

IPC分类号： G11C700

CPC分类号： G11C29/70

摘要： An input protective circuit in a semiconductor integrated circuit device includes a bipolar transistor arranged for an interconnection layer. An N-type active region in the bipolar transistor is connected to an electrode of a program element. The electrode is connected to the interconnection layer. The interconnection layer supplies a high voltage for breaking a dielectric of a program element. A voltage on a P-type well is externally adjusted via a resistance element. Thereby, erroneous program due to serge entering at the interconnection layer can be avoided.

摘要翻译： 半导体集成电路器件中的输入保护电路包括布置成互连层的双极晶体管。 双极晶体管中的N型有源区连接到程序元件的电极。 电极连接到互连层。 互连层提供用于断开程序元件的电介质的高电压。 通过电阻元件外部调整P型阱上的电压。 因此，可以避免由于在互连层处进入的错误程序。

公开(公告)号：US06466509B1

公开(公告)日：2002-10-15

申请号：US10050131

申请日：2002-01-18

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C11/4087 ,  G11C2207/104

摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.

摘要翻译： 第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有 第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带 第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。

公开(公告)号：US06421286B1

公开(公告)日：2002-07-16

申请号：US09978819

申请日：2001-10-18

申请人： Jun Ohtani ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Tomoya Kawagoe

发明人： Jun Ohtani ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Tomoya Kawagoe

IPC分类号： G11C700

CPC分类号： G11C29/72 ,  G11C29/44

摘要： Built-in self-test circuit and built-in redundancy analysis circuit are provided commonly to plural DRAM cores. Built-in redundancy analysis circuit determines a defective address to be replaced with one of plural spare memory cell rows and plural spare memory cell columns according to an address signal and a detection result of a defective memory cell from built-in self-test circuit. Built-in redundancy analysis circuit controls an effective service area of an address storage circuit into which a defective address is stored according to a capacity of a DRAM core to be tested.

摘要翻译： 内置自检电路和内置冗余分析电路通常提供给多个DRAM内核。 内置冗余分析电路根据地址信号和内置的自检电路中的有缺陷的存储单元的检测结果来确定要被多个备用存储单元行和多个备用存储单元列中的一个替换的缺陷地址。 内置冗余分析电路根据要测试的DRAM内核的容量来控制存储有缺陷地址的地址存储电路的有效服务区域。

公开(公告)号：US06411560B1

公开(公告)日：2002-06-25

申请号：US09987277

申请日：2001-11-14

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C514

CPC分类号： G11C7/1096 ,  G11C5/146 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4074

摘要： A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.

摘要翻译： 第一电源电压被提供给读出放大器的电源节点。 位线驱动器将由第二电源电压组成的列选择信号输出到GIO线路电路的N沟道MOS晶体管的栅极端子。 当输入/输出数据为[1]时，低于第一电源电压的第三电源电压被提供给全局数据线。 在这种情况下，利用所使用的N沟道MOS晶体管的阈值电压，建立关系：第二电源电压<=第三电源电压+阈值电压。 结果，在由具有不同电压电平的多个电源电压驱动的半导体存储器件中，可以减小泄漏电流。

公开(公告)号：US06407958B2

公开(公告)日：2002-06-18

申请号：US09817032

申请日：2001-03-27

申请人： Hiroshi Kato ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroshi Kato ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C700

CPC分类号： G11C11/4074 ,  G11C8/12 ,  G11C29/846

摘要： In an SDRAM, a column decoder is split into four blocks, and a specific predecode signal is allocated to each block. A sub power supply line is provided in correspondence to each block, and a P-channel MOS transistor, having a relatively high threshold voltage, rendered conductive in response to the corresponding predecode signal is connected between the sub power supply line and a main power supply line. A power supply potential is supplied to only a selected block, for reducing a leakage current.

摘要翻译： 在SDRAM中，列解码器被分成四个块，并且将特定的预解码信号分配给每个块。 提供与每个块对应的副电源线，并且具有相对于相应的预解码信号导通的具有相对高阈值电压的P沟道MOS晶体管连接在副电源线和主电源 线。 电源电位只提供给选定的块，以减少漏电流。