公开(公告)号：US20250013518A1

公开(公告)日：2025-01-09

申请号：US18892677

申请日：2024-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F11/07 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F11/27 ,  G06F11/30 ,  G06F11/36 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/16

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US12159030B2

公开(公告)日：2024-12-03

申请号：US18243809

申请日：2023-09-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Matthew David Pierson ,  David E. Smith ,  Timothy David Anderson

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F12/0846 ,  G06F12/0862

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

公开(公告)号：US20240265062A1

公开(公告)日：2024-08-08

申请号：US18633703

申请日：2024-04-12

Applicant: Texas Instruments Incorporated

Inventor： Arthur John Redfern ,  Timothy David Anderson ,  Kai Chirca ,  Chenchi Luo ,  Zhenhua Yu

IPC: G06F17/16 ,  G06F17/14 ,  G06N3/045 ,  G06N3/063

CPC classification number: G06F17/16 ,  G06F17/141 ,  G06N3/045 ,  G06N3/063

Abstract: A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.

公开(公告)号：US11789872B2

公开(公告)日：2023-10-17

申请号：US17384864

申请日：2021-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson

IPC: G06F12/08 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F9/38

CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F12/0862 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0886 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028 ,  Y02D10/00

Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

公开(公告)号：US20230048071A1

公开(公告)日：2023-02-16

申请号：US17971691

申请日：2022-10-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson ,  Kai Chirca

IPC: G06F21/78 ,  G06F12/0815 ,  G06F21/79 ,  G06F12/14 ,  G06F12/0817 ,  G06F13/16 ,  G06F13/30 ,  G06F12/0831 ,  H04L9/40 ,  G06F13/42 ,  G06F12/1081 ,  G06F13/28 ,  G06F13/40 ,  G06F12/0842

Abstract: Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

公开(公告)号：US11573847B2

公开(公告)日：2023-02-07

申请号：US16988500

申请日：2020-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/36 ,  G06F11/10

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US11573802B2

公开(公告)日：2023-02-07

申请号：US17079038

申请日：2020-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca

IPC: G06F9/38 ,  G06F9/54 ,  G06F11/36 ,  G06F9/30 ,  G06F9/48

Abstract: A method includes asserting a field of an event flag mask register configured to inhibit an event handler. The method also includes, responsive to an event that corresponds to the field of the event flag mask register being triggered: asserting a field of an event flag register associated with the event; and based the field in the event flag register being asserted, taking an action by a task being executed by the data processor core.

公开(公告)号：US20220326954A1

公开(公告)日：2022-10-13

申请号：US17849994

申请日：2022-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  David E. Smith, JR. ,  Paul D. Gauvreau

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-implemented method includes fetching a fetch-packet containing a first hyper-block from a first address of a memory, the fetch-packet containing a bitwise distance from an entry point of the first hyper-block to a predicted exit point; executing a first branch instruction of the first hyper-block, wherein the first branch instruction corresponds to a first exit point, and wherein the first branch instruction includes an address corresponding to an entry point of a second hyper-block; storing, responsive to executing the first branch instruction, a bitwise distance from the entry point of the first hyper-block to the first exit point; and moving a program counter from the first exit point of the first hyper-block to the entry point of the second hyper-block.

公开(公告)号：US11429526B2

公开(公告)日：2022-08-30

申请号：US16653221

申请日：2019-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David Pierson ,  Kai Chirca ,  Daniel Wu

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

公开(公告)号：US20220137972A1

公开(公告)日：2022-05-05

申请号：US17578516

申请日：2022-01-19

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Paul Daniel Gauvreau ,  David Edward Smith, JR.

IPC: G06F9/32 ,  G06F9/38

Abstract: An integrated circuit comprising instruction processing circuitry for processing a plurality of program instructions and instruction prediction circuitry. The instruction prediction circuitry comprises circuitry for detecting successive occurrences of a same program loop sequence of program instructions. The instruction prediction circuitry also comprises circuitry for predicting a number of iterations of the same program loop sequence of program instructions, in response to detecting, by the circuitry for detecting, that a second occurrence of the same program loop sequence of program instructions comprises a same number of iterations as a first occurrence of the same program loop sequence of program instructions.