公开(公告)号：US07943462B1

公开(公告)日：2011-05-17

申请号：US12894579

申请日：2010-09-30

申请人： Sven Beyer ,  Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski

发明人： Sven Beyer ,  Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/28238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device.

摘要翻译： 当在早期制造阶段形成复杂的高k金属栅电极结构时，可以基于碳间隔元件有效地去除栅电极结构的电介质盖层，这可以保持氮化硅间隔结构的完整性 。 此后，可以基本上除去牺牲碳隔离物而不影响其它器件区域，例如隔离结构，有源区等，这可能有助于在半导体器件的进一步处理期间优良的工艺条件。

公开(公告)号：US09048336B2

公开(公告)日：2015-06-02

申请号：US13186813

申请日：2011-07-20

申请人： Thilo Scheiper ,  Jan Hoentschel ,  Steven Langdon

发明人： Thilo Scheiper ,  Jan Hoentschel ,  Steven Langdon

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/28 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12 ,  H01L29/51

CPC分类号： H01L21/26506 ,  H01L21/266 ,  H01L21/2822 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517

摘要： Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.

摘要翻译： 复杂晶体管的性能和/或均匀性可以通过在形成复杂的高k金属栅电极结构之前在晶体管的有源区中引入碳物种来增强。 例如，在选择性地形成用于P沟道晶体管的阈值调节半导体材料之后，可以通过离子注入将碳物质并入P沟道晶体管和N沟道晶体管的有源区，而N的有源区 通道晶体管仍然被掩蔽。

公开(公告)号：US08698243B2

公开(公告)日：2014-04-15

申请号：US13953349

申请日：2013-07-29

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.

摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。

公开(公告)号：US20130320449A1

公开(公告)日：2013-12-05

申请号：US13482393

申请日：2012-05-29

申请人： Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L21/8238 ,  H01L27/088 ,  H01L21/336

CPC分类号： H01L27/0922 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/458 ,  H01L29/4925 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

公开(公告)号：US20130295767A1

公开(公告)日：2013-11-07

申请号：US13462246

申请日：2012-05-02

申请人： Thilo Scheiper ,  Peter Baars

发明人： Thilo Scheiper ,  Peter Baars

IPC分类号： H01L21/28 ,  H01L21/3065

CPC分类号： H01L21/823807 ,  H01L21/0206 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance.

摘要翻译： 当基于形成在晶体管上方的高应力电介质材料形成复杂的晶体管时，通过在沉积高应力材料之前减小栅电极结构的间隔结构的尺寸，可以增加应力传递效率。 在沉积高应力材料之前，可以实施额外的清洁工艺，以减少任何金属污染物的存在，特别是在栅电极结构附近，否则会导致增加的边缘电容。

公开(公告)号：US20130256901A1

公开(公告)日：2013-10-03

申请号：US13436323

申请日：2012-03-30

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/768 ,  H01L23/48 ,  B82Y40/00

CPC分类号： H01L21/76816 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.

摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。

公开(公告)号：US20130244388A1

公开(公告)日：2013-09-19

申请号：US13421604

申请日：2012-03-15

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Shesh Mani Pandey

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Shesh Mani Pandey

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成栅叠层。 在该方法中，在第一剂量的掺杂剂离子的半导体衬底上进行第一晕圈注入，以在其中形成第一晕圈。 在栅堆叠周围形成第二晕环。 然后在第二剂量的掺杂剂离子的半导体衬底上进行第二晕圈注入，以在其中形成第二晕圈。

公开(公告)号：US08508001B2

公开(公告)日：2013-08-13

申请号：US13217792

申请日：2011-08-25

申请人： Steven Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Steven Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L27/14 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78654

摘要： Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.

摘要翻译： 本文公开了一种半导体器件，其包括半导体衬底和至少部分地位于半导体衬底中的功函数调整层，所述功函数调整层具有中间部分，相对端部和靠近所述相对的每一个的端部区域 端部和位于功函调整层上方的栅电极。 每个端部区域的最大厚度比工作功能调节层的中间部分的平均厚度大至少25％。

公开(公告)号：US08455314B2

公开(公告)日：2013-06-04

申请号：US13117249

申请日：2011-05-27

申请人： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

发明人： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC分类号： H01L21/8238

CPC分类号： H01L29/7827 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

摘要翻译： 在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过 形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。

公开(公告)号：US08409942B2

公开(公告)日：2013-04-02

申请号：US12914570

申请日：2010-10-28

申请人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28105 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659

摘要： In a replacement gate approach, a spacer may be formed in the gate opening after the removal of the placeholder material, thereby providing a superior cross-sectional shape upon forming any electrode metals in the gate opening. Moreover, the spacer may be used for reducing the gate length, while not requiring more complex gate patterning strategies.

摘要翻译： 在替代门方法中，在移除占位符材料之后，可以在闸门开口中形成间隔件，从而在门开口中形成任何电极金属时提供优异的横截面形状。 此外，间隔物可以用于减小栅极长度，而不需要更复杂的栅极图案化策略。