Register reservation method for fast context switching in microprocessors
    61.
    发明授权
    Register reservation method for fast context switching in microprocessors 失效
    微处理器快速上下文切换的注册预约方法

    公开(公告)号:US5987258A

    公开(公告)日:1999-11-16

    申请号:US883137

    申请日:1997-06-27

    CPC classification number: G06F9/462

    Abstract: Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler option which commands the compiler to not use a given set of registers in the compiled code. Post-processing is then performed on the compiled interrupt code to replace accesses to a first set of registers with accesses to the given set of registers. The result is that while both the main program and the interrupt handler were written in C, the compiled code for each employs different registers. This allows context switching from the main program to the interrupt handler and back again with almost none of the overhead traditionally associated with context switching register save and restore operations during exception handling.

    Abstract translation: 微处理器主程序及其中断处理例程以高级编程语言(如C)编写。每个编译单独编译,每个编译调用编译器选项,命令编译器在编译代码中不使用给定的一组寄存器。 然后对编译的中断代码进行后处理,以通过访问给定的寄存器组来替换对第一组寄存器的访问。 结果是当主程序和中断处理程序都用C编写时,每个编译代码使用不同的寄存器。 这允许从主程序到中断处理程序的上下文切换,并且在异常处理期间几乎没有传统上与上下文切换寄存器保存和恢复操作相关联的开销。

    ATM communication system interconnect/termination unit

    公开(公告)号:US5982749A

    公开(公告)日:1999-11-09

    申请号:US612112

    申请日:1996-03-07

    Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

    Scheduler design for ATM switches, and its implementation in a
distributed shared memory architecture
    63.
    发明授权
    Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture 失效
    ATM交换机的调度器设计及其在分布式共享存储器架构中的实现

    公开(公告)号:US5959993A

    公开(公告)日:1999-09-28

    申请号:US714005

    申请日:1996-09-13

    Abstract: A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.

    Abstract translation: 一种用于分布式共享存储器交换机架构的小区调度器,其包括用于根据若干不同调度模式之一调度来自交换机结构的输出队列的小区的传输的控制器。 控制器接收模式选择输入,将输出队列隔离成组,为组分配优先级排序,并根据模式选择输入和优先级排序确定每组输出队列中的调度规则之一。 输出队列组包括一组每个虚拟通道(VC)队列和至少一组先入先出(FIFO)队列。 调度规则包括控制器在每个VC队列组中应用的加权公平排队(WFQ)调度规则,以及控制器在至少一组FIFO队列中应用的循环(RR)调度规则。 优先级排名包括分配给每个VC队列组的最高优先级排名。

    ATM communication system interconnect/termination unit

    公开(公告)号:US5920561A

    公开(公告)日:1999-07-06

    申请号:US614806

    申请日:1996-03-07

    CPC classification number: H04Q11/0478 H04L2012/5616

    Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

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