公开(公告)号：US08436366B2

公开(公告)日：2013-05-07

申请号：US13131369

申请日：2010-04-06

申请人： Shin Harada ,  Makoto Sasaki ,  Takeyoshi Masuda

发明人： Shin Harada ,  Makoto Sasaki ,  Takeyoshi Masuda

IPC分类号： H01L29/15 ,  H01L29/04

CPC分类号： H01L29/7802 ,  B24B7/17 ,  B24B7/228 ,  B24B37/08 ,  B24B37/10 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/02 ,  H01L29/045 ,  H01L29/063 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122 ,  H01L29/8128 ,  H01L29/8611 ,  H01L29/872

摘要： A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than −40 μm and not greater than −5 μm, and a value for warp at the main surface being not smaller than 5 μm and not greater than 40 μm. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.

摘要翻译： 获得由于基板的弯曲，具有薄膜的基板和形成有上述基板的半导体器件导致的半导体器件的加工精度的抑制劣化的基板以及上述制造半导体器件的方法。 根据本发明的基底具有直径为2英寸或更大的主表面，主表面的弓形值不小于-40μm且不大于-5μm，并且在该表面处的翘曲值 主表面不小于5μm，不大于40μm。 优选地，基板的主表面的表面粗糙度Ra的值不大于1nm，并且主表面的表面粗糙度Ra的值不大于100nm。

公开(公告)号：US20130109110A1

公开(公告)日：2013-05-02

申请号：US13807197

申请日：2011-07-06

申请人： Makoto Sasaki ,  Shin Harada ,  Satomi Itoh ,  Kyoko Okita

发明人： Makoto Sasaki ,  Shin Harada ,  Satomi Itoh ,  Kyoko Okita

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802 ,  Y10S438/931

摘要： A silicon carbide substrate is made of silicon carbide. In the silicon carbide substrate, a normal line of one main surface of the silicon carbide substrate and a normal line of a {03-38} plane form an angle of 0.5° or smaller in an orthogonal projection to a plane including a direction and a direction. In this way, there can be provided the silicon carbide substrate allowing for both improvement of channel mobility of a semiconductor device and stable characteristics thereof.

摘要翻译： 碳化硅衬底由碳化硅制成。 在碳化硅衬底中，碳化硅衬底的一个主表面的法线和{03-38}面的法线在垂直投影中形成0.5°或更小的角度，该平面包括<01- 10>方向和<0001>方向。 以这种方式，可以提供碳化硅衬底，其允许改善半导体器件的沟道迁移率和其稳定特性。

公开(公告)号：US20110180813A1

公开(公告)日：2011-07-28

申请号：US13122353

申请日：2010-03-23

申请人： Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

发明人： Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/24 ,  H01L29/739

CPC分类号： H01L29/7395 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

摘要： An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.

摘要翻译： 能够通过降低沟道迁移率而降低导通电阻的IGBT包括：由SiC制成的n型衬底，其主表面相对于平面取向具有不小于50度且不大于65度的偏离角 {0001}; 由SiC制成的p型反向击穿电压保持层，形成在基板的主表面上; 形成为包括反向击穿电压保持层的第二主表面的n型阱区; 在所述阱区域中形成的包括所述第二主表面并且包含浓度高于所述反向击穿电压保持层的p型杂质的发射极区域; 形成在反向击穿电压保持层上的栅极氧化膜; 以及形成在栅氧化膜上的栅电极。 在包括阱区和栅极氧化膜之间的界面的区域中，形成高浓度氮区，使得氮浓度高于阱区和栅极氧化膜的氮浓度。

公开(公告)号：US20110175110A1

公开(公告)日：2011-07-21

申请号：US13120890

申请日：2010-03-23

申请人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

发明人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

IPC分类号： H01L29/24 ,  H01L21/336 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

摘要： A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.

摘要翻译： MOSFET包括碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 当绝缘膜的厚度不小于30nm且不大于46nm时，其阈值电压不大于2.3V。 当绝缘膜的厚度大于46nm且不大于100nm时，其阈值电压大于2.3V且不大于4.9V。

公开(公告)号：US20110031505A1

公开(公告)日：2011-02-10

申请号：US12936589

申请日：2009-02-03

申请人： Shin Harada ,  Masato Tsumori

发明人： Shin Harada ,  Masato Tsumori

IPC分类号： H01L29/24 ,  H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02516 ,  H01L21/02529 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/861

摘要： A silicon carbide semiconductor device having an active layer with reduced defect density which is formed on a substrate made of silicon carbide, and a method of manufacturing the same are provided. A semiconductor device includes a substrate made of silicon carbide and having an off angle of not less than 50° and not more than 65° with respect to a plane orientation; a buffer layer, and an epitaxial layer, a p-type layer and an n+ region each serving as an active layer. The buffer layer is made of silicon carbide and formed on the substrate. The active layer is made of silicon carbide and formed on the buffer layer. The micropipe density is lower in the active layer than in the substrate. The density of dislocations in which the direction of a Burgers vector corresponds to is higher in the active layer than in the substrate.On the film forming conditions in the step of forming the buffer layer, the composition and the flow rate of the material gas is determined such that the value of the C/Si ratio representing a ratio of carbon atoms to silicon atoms in the material gas used for forming the buffer layer is smaller than the value of the C/Si ratio in the step of forming the active layer.

摘要翻译： 提供一种碳化硅半导体器件及其制造方法，该碳化硅半导体器件具有形成在由碳化硅制成的衬底上的具有降低的缺陷密度的有源层。 半导体器件包括由碳化硅制成并且相对于平面取向具有不小于50°并且不超过65°的偏离角的衬底; 缓冲层，外延层，p型层和n +区，各自用作有源层。 缓冲层由碳化硅制成并形成在基底上。 有源层由碳化硅制成并形成在缓冲层上。 活性层中的微管密度比底物中的微管密度低。 汉堡矢量方向对应的位错密度在活性层中高于底物。 在形成缓冲层的步骤中的成膜条件下，确定原料气体的组成和流速，使得表示所使用的原料气体中的碳原子与硅原子的比率的C / Si比值 用于形成缓冲层的步骤小于在形成有源层的步骤中的C / Si比的值。

公开(公告)号：US20110001144A1

公开(公告)日：2011-01-06

申请号：US12919992

申请日：2009-12-11

申请人： Kuzuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

发明人： Kuzuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

IPC分类号： H01L31/0312 ,  H01L21/337

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/8083

摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。 晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。 第一p型区域包括设置成包括上表面的基极区域和突出区域。 基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。 栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

公开(公告)号：US20100318485A1

公开(公告)日：2010-12-16

申请号：US12867205

申请日：2009-02-09

申请人： Shin Harada ,  Shinya Ishikawa ,  Takashi Shiraki

发明人： Shin Harada ,  Shinya Ishikawa ,  Takashi Shiraki

IPC分类号： G06N5/02 ,  G06F15/16 ,  G06F17/30

CPC分类号： G06Q30/02

摘要： An information distribution system which can distribute information efficiently. The information distribution apparatus (300) identifies an intermediary (200) for distributing information to the terminal (100) of the party to whom the information is to be distributed. Subsequently, a request to distribute information to the terminal (100) of the party to whom the information is to be distributed is submitted to the terminal (200) of the identified intermediary. Therein, the information distribution apparatus (300) selects a party who has a relationship with the party to whom the information is to be distributed as the intermediary (200).An information distribution system capable of performing an efficient information distribution is provided.

摘要翻译： 一种可以有效分发信息的信息分发系统。 信息分配装置（300）识别用于将信息分发给要分发信息的一方的终端（100）的中介（200）。 随后，向所识别的中介的终端（200）提交向信息分发的一方的终端（100）分发信息的请求。 其中，信息分发装置（300）选择与作为中间体（200）分发信息的一方有关系的一方。 提供能够执行有效的信息分发的信息分配系统。

公开(公告)号：US20070278540A1

公开(公告)日：2007-12-06

申请号：US11770414

申请日：2007-06-28

申请人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

发明人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/66068 ,  H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66909 ,  H01L29/8083

摘要： A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

摘要翻译： 根据本发明的垂直JFET1a具有n +型漏极半导体部分2，n型漂移半导体部分3，p +型栅极半导体部分4 ，n型沟道半导体部分5，n + +型源极半导体部分7和ap + +型栅极半导体部分8。 n型漂移半导体部分3放置在n +型漏极半导体部分2的主表面上，并且具有沿与主表面相交的方向延伸的第一至第四区域3至3d 。 p型+ +型栅极半导体部分4放置在n型漂移半导体部分3的第一至第三区域3至3c上。 n型沟道半导体部分5沿着p + +型栅极半导体部分4放置，并与n型漂移半导体部分3的第四区域3d电连接。

公开(公告)号：US20070225025A1

公开(公告)日：2007-09-27

申请号：US11724179

申请日：2007-03-15

申请人： Kazuhiro Takahashi ,  Yoshihiro Ono ,  Shin Harada ,  Takashi Shiraki ,  Takehiko Kashiwagi ,  Junpei Kamimura

发明人： Kazuhiro Takahashi ,  Yoshihiro Ono ,  Shin Harada ,  Takashi Shiraki ,  Takehiko Kashiwagi ,  Junpei Kamimura

IPC分类号： H04B7/00

CPC分类号： H04W4/08 ,  H04L67/14 ,  H04L67/24 ,  H04W4/10 ,  H04W76/45 ,  H04W84/08

摘要： The present invention provides a communication system, a control apparatus, a program and a recording medium that controls participation in a session using presence information on participation member and information of the session itself. A communication system in which a plurality of communication terminals are connected to each other through a network to establish communication between the communication terminals has a presence information registering section that registers presence information of the communication terminals, a participation condition setting section that sets a participation condition for participating in the communication, a communication information managing section that manages communication information related to a state of the communication, and a communication control section that controls participation in and separation from the communication of the communication terminals.

摘要翻译： 本发明提供了一种通信系统，控制装置，程序和记录介质，其使用关于参与成员的存在信息和会话本身的信息来控制对会话的参与。 其中多个通信终端通过网络彼此连接以在通信终端之间建立通信的通信系统具有登记通信终端的存在信息的存在信息登记部分，设置参与条件的参与条件设置部分 用于参与通信的通信信息管理部分，其管理与通信状态相关的通信信息;以及通信控制部分，其控制参与通信终端的通信并与其分离。

公开(公告)号：US08803294B2

公开(公告)日：2014-08-12

申请号：US13529602

申请日：2012-06-21

申请人： Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

发明人： Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

摘要： A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.

摘要翻译： 衬底具有由具有多晶型4H的六方晶单晶结构的半导体制成的表面。 基板的表面通过交替地提供具有（0-33-8）的平面取向的第一平面和连接到第一平面并具有不同于第一平面的平面取向的平面取向的第二平面来构造。 栅极绝缘膜设置在基板的表面上。 在栅极绝缘膜上设置栅电极。