公开(公告)号：US07244992B2

公开(公告)日：2007-07-17

申请号：US10727550

申请日：2003-12-05

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US07205641B2

公开(公告)日：2007-04-17

申请号：US11017053

申请日：2004-12-21

申请人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

发明人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L31/075

CPC分类号： H01L31/03529 ,  H01L27/0255 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L31/02019 ,  H01L31/105 ,  Y02E10/50

摘要： An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

摘要翻译： 用于将入射光信号转换成电信号的集成电路装置包括半导体衬底，形成在半导体衬底内部的阱区，形成在阱区上的电介质层和用于接收入射光信号的多晶硅层，形成 包括p型部分，n型部分和设置在p型和n型部分之间的未掺杂部分，其中阱区被偏置以控制多晶硅层以提供电信号 。

公开(公告)号：US20060256489A1

公开(公告)日：2006-11-16

申请号：US11126134

申请日：2005-05-10

申请人： Ming-Dou Ker ,  Cheng-Ming Lee

发明人： Ming-Dou Ker ,  Cheng-Ming Lee

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H03F1/52 ,  H03F3/195 ,  H03F3/60 ,  H03F2200/441 ,  H03F2200/444 ,  H03F2200/451

摘要： An ESD protection circuit with impedance matching for radio frequency integrated circuits is provided. Nodes at the ends of a transmission line, respectively have at least one ESD component coupled between each and one of the power rails. The ESD components discharge ESD currents and the transmission lines provide RF matching.

摘要翻译： 提供了一种具有射频集成电路阻抗匹配的ESD保护电路。 在传输线的端部处的节点分别具有耦合在每个和一个电源轨道之间的至少一个ESD部件。 ESD元件放电ESD电流，传输线提供RF匹配。

公开(公告)号：US20060231896A1

公开(公告)日：2006-10-19

申请号：US11451344

申请日：2006-06-13

申请人： Ming-Dou Ker ,  Chih-Kang Deng ,  Tang-Kui Tseng ,  An Shih ,  Sheng-Chieh Yang

发明人： Ming-Dou Ker ,  Chih-Kang Deng ,  Tang-Kui Tseng ,  An Shih ,  Sheng-Chieh Yang

IPC分类号： H01L23/62

CPC分类号： H01L27/1233 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/1214 ,  H01L29/0657

摘要： An ESD protection device with thicker polysilicon film, an electronic apparatus having the same, and a method for manufacturing the same are provided. The ESD protection device can be a diode or a MOS transistor with a thicker polysilicon film employed in an ESD protection circuit to protect an electronic apparatus. The electronic apparatus includes a substrate having a device area and an ESD protection circuit area. A first polysilicon film of a first thickness is formed on the device area of the substrate, so as to form an electronic device. A second polysilicon film of a second thickness is formed on the ESD protection circuit area, so as to form an ESD protection device. The second thickness, which is preferably about in the range of 100 to 500 nanometers, is thicker than the first thickness.

摘要翻译： 提供具有较厚多晶硅膜的ESD保护器件，具有该多晶硅膜的电子设备及其制造方法。 ESD保护器件可以是用于ESD保护电路中的较厚多晶硅膜的二极管或MOS晶体管，以保护电子设备。 电子设备包括具有器件区域和ESD保护电路区域的衬底。 在衬底的器件区域上形成第一厚度的第一多晶硅膜，以形成电子器件。 在ESD保护电路区域上形成第二厚度的第二多晶硅膜，以形成ESD保护器件。 第二厚度优选地在100至500纳米的范围内比第一厚度厚。

公开(公告)号：US07064942B2

公开(公告)日：2006-06-20

申请号：US10440083

申请日：2003-05-19

申请人： Ming-Dou Ker ,  Wen-Yu Lo

发明人： Ming-Dou Ker ,  Wen-Yu Lo

IPC分类号： H02H9/00

CPC分类号： H01L27/0285 ,  H02H9/046

摘要： An ESD protection circuit with tunable gate-bias coupled between a first and second pads for receiving power supply voltages. The ESD protection circuit includes a diode, a resistor coupled between the cathode of the diode and the first pad, a capacitor coupled between the cathode of the diode and the second pad, a first transistor of a first conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the second pad, a second transistor of a second conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the first pad, and a third transistor of the first conductivity type having a gate coupled to the anode of the diode, a drain coupled to the first pad and a source coupled to the second pad.

摘要翻译： 具有耦合在第一和第二焊盘之间的可调门限偏压的ESD保护电路，用于接收电源电压。 ESD保护电路包括二极管，耦合在二极管的阴极和第一焊盘之间的电阻器，耦合在二极管的阴极和第二焊盘之间的电容器，第一导电类型的第一晶体管，其栅极耦合到 二极管的阴极，耦合到二极管的阳极的漏极和耦合到第二焊盘的源极，具有耦合到二极管的阴极的栅极的第二导电类型的第二晶体管，耦合到二极管的阳极的漏极 二极管和耦合到第一焊盘的源，以及第一导电类型的第三晶体管，其具有耦合到二极管的阳极的栅极，耦合到第一焊盘的漏极和耦合到第二焊盘的源极。

公开(公告)号：US07046036B2

公开(公告)日：2006-05-16

申请号：US10790733

申请日：2004-03-03

申请人： Shih-Lun Chen ,  Ming-Dou Ker

发明人： Shih-Lun Chen ,  Ming-Dou Ker

IPC分类号： H03K19/02

CPC分类号： H03K3/356113 ,  H03K17/102 ,  H03K19/00315

摘要： An output buffer circuit with low-voltage devices to driver high-voltage signals for PCI-X applications is proposed. Because power supply voltage of PCI-X is at 3.3V, the high-voltage gate-oxide stress is a serious problem to design PCI-X I/O circuit in a 0.13 μm 1V/2.5V CMOS process with only low-voltage gate oxide. This proposed output buffer circuit can be operated at 133 MHz in 3.3V PCI-X environment without causing high-voltage gate-oxide reliability problem. In this design, the circuit is implemented in a 0.13 μm 1V/2.5V CMOS process and the output signal swing can be 3.3V. Besides, a level converter that converts 0V˜1V voltage swing to 1V˜3.3V voltage swing is also presented.

摘要翻译： 提出了一种具有低电压器件的驱动器用于PCI-X应用的高电压信号的输出缓冲电路。 由于PCI-X的电源电压为3.3V，高压栅极氧化应力是在0.13 mum 1V / 2.5V CMOS工艺中设计PCI-X I / O电路的严重问题，只有低压栅极 氧化物。 该提出的输出缓冲电路可以在3.3V PCI-X环境中工作在133 MHz，而不会导致高压栅氧化可靠性问题。 在这种设计中，电路采用0.13 mum 1V / 2.5V CMOS工艺，输出信号摆幅可以为3.3V。 此外，还提出了将0V〜1V电压摆幅转换为1V〜3.3V的电压摆幅的电平转换器。

公开(公告)号：US07038276B2

公开(公告)日：2006-05-02

申请号：US10434169

申请日：2003-05-09

申请人： Ming-Dou Ker ,  Wen-Hsia Kung ,  Ya-Hsiang Tai

发明人： Ming-Dou Ker ,  Wen-Hsia Kung ,  Ya-Hsiang Tai

IPC分类号： H01L29/76

CPC分类号： H01L29/78615

摘要： A thin-film transistor (TFT) with body contacts is disclosed. It is used in polysilicon TFT LCD's. A body contact region for separating the gate electrode, a source region, and a drain region is made in the TFT. Through the dopants in the body contact region and different impurities in the source region and the drain region, a body-trigger bias is imposed on the body of the TFT. This method reduces the threshold voltage of the TFT driving circuit, thereby increasing the driving current.

摘要翻译： 公开了一种具有体触点的薄膜晶体管（TFT）。 它用于多晶硅TFT LCD。 在TFT中制造用于分离栅电极，源极区和漏极区的体接触区域。 通过体接触区域中的掺杂剂和源极区域和漏极区域中的不同杂质，对TFT的主体施加体触发偏置。 该方法降低了TFT驱动电路的阈值电压，从而增加了驱动电流。

公开(公告)号：US20060044719A1

公开(公告)日：2006-03-02

申请号：US11205378

申请日：2005-08-17

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L29/7436

摘要： Diode strings and electrostatic discharge circuits characterized by low current leakage. Each diode region provides a diode and has first and second regions. The first region is of a first conductive type and formed on a substrate, acting as a first electrode of a diode. The second region is of a second conductive type opposite to the first conductive type, formed in the first region and acting as a second electrode of a corresponding diode. The diodes are forward connected in series to form major anode and cathode of the diode string. An isolation region is of the second conductive type to isolate those diode regions. A bias resistor is connected between the isolation region and a first power line. During normal operation, the voltage of the first power line is not within the range between the voltages of the major anode and cathode.

公开(公告)号：US20060027873A1

公开(公告)日：2006-02-09

申请号：US11240475

申请日：2005-10-03

申请人： Ming-Dou Ker ,  Hsin-Chyh Hsu ,  Wen-Yu Lo

发明人： Ming-Dou Ker ,  Hsin-Chyh Hsu ,  Wen-Yu Lo

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

公开(公告)号：US20050270710A1

公开(公告)日：2005-12-08

申请号：US10857836

申请日：2004-06-02

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L27/02 ,  H01L29/74 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： The present invention relates to an SCR (Silicon Controlled Rectifier) for the ESD (electrostatic discharge) protection comprising two terminal electrodes of a first electrode and a second electrode, a PMOS, an NMOS and an SCR structure. By utilizing an embedded SCR, a whole-chip ESD protection circuit design can be obtained. The present invention is suitable for IC products, and for applications by IC design industries and IC foundry industries.

摘要翻译： 本发明涉及一种用于ESD（静电放电）保护的SCR（硅控整流器），其包括第一电极和第二电极，PMOS，NMOS和SCR结构的两个端电极。 通过利用嵌入式SCR，可以获得全芯片ESD保护电路设计。 本发明适用于IC产品，适用于IC设计行业和IC铸造行业。