公开(公告)号：US20190081150A1

公开(公告)日：2019-03-14

申请号：US16178580

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/49 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/7843

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US10205005B1

公开(公告)日：2019-02-12

申请号：US15691717

申请日：2017-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/24 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/08

Abstract: A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

公开(公告)号：US10153369B2

公开(公告)日：2018-12-11

申请号：US15627427

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.

公开(公告)号：US10153034B2

公开(公告)日：2018-12-11

申请号：US15448599

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11 ,  G11C11/417 ,  G11C11/412

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US20180247005A1

公开(公告)日：2018-08-30

申请号：US15462900

申请日：2017-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method for a semiconductor layout pattern decomposition includes following steps. (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition to the semiconductor layout pattern to obtain a grille pattern and a non-grille pattern; (c) recognizing a plurality of intersection regions in the grille pattern and alternately marking the intersection regions with a first region and a second region; (d) performing a second separation/decomposition to the grille pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns perpendicular to each other, the first sub-patterns including the first regions, the second sub-patterns including the second regions; and (e) introducing a plurality of first assistance features on the first regions in the first sub-patterns and on the second regions on the second regions in the second sub-patterns, respectively. The step (a) to the step (e) are implemented using a computer.

公开(公告)号：US20180218917A1

公开(公告)日：2018-08-02

申请号：US15423544

申请日：2017-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Hon-Huei Liu ,  Chia-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/66

Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.

公开(公告)号：US20180151371A1

公开(公告)日：2018-05-31

申请号：US15880506

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/283 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/31 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/283 ,  H01L21/308 ,  H01L21/31 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/845

Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.

公开(公告)号：US20180144988A1

公开(公告)日：2018-05-24

申请号：US15861692

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.

公开(公告)号：US20180061963A1

公开(公告)日：2018-03-01

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US09837511B2

公开(公告)日：2017-12-05

申请号：US15403187

申请日：2017-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/335 ,  H01L21/225 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.