中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

105 records (took 0.045 seconds)

    MAGNETORESISTIVE RANDOM ACCESS MEMORY
    62.
    发明公开
    MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20240090234A1

    公开(公告)日：2024-03-14

    申请号：US18512058

    申请日：2023-11-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

    IPC: H10B61/00 ,  G11C7/18 ,  H10N50/80

    CPC classification number: H10B61/20 ,  G11C7/18 ,  H10N50/80

    Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

    One-time programmable memory device
    63.
    发明授权
    One-time programmable memory device 有权

    公开(公告)号：US11778814B2

    公开(公告)日：2023-10-03

    申请号：US17329171

    申请日：2021-05-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

    IPC: H10B20/20 ,  H01L29/423 ,  H10B10/00

    CPC classification number: H10B20/20 ,  H01L29/42364 ,  H10B10/18

    Abstract: A semiconductor device includes a substrate having an input/output (I/O) region, an one time programmable (OTP) capacitor region, and a core region, a first metal gate disposed on the I/O region, a second metal gate disposed on the core region, and a third metal gate disposed on the OTP capacitor region. Preferably, the first metal gate includes a first high-k dielectric layer, the second metal gate includes a second high-k dielectric layer, and the first high-k dielectric layer and the second high-k dielectric layer include an I-shape.

    ONE-TIME PROGRAMMABLE MEMORY CELL
    64.
    发明公开
    ONE-TIME PROGRAMMABLE MEMORY CELL 审中-公开

    公开(公告)号：US20230247827A1

    公开(公告)日：2023-08-03

    申请号：US18134041

    申请日：2023-04-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

    IPC: H10B20/25

    CPC classification number: H10B20/25

    Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

    SEMICONDUCTOR MEMORY STRUCTURE AND FABRICATION METHOD THEREOF
    69.
    发明申请
    SEMICONDUCTOR MEMORY STRUCTURE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20230081533A1

    公开(公告)日：2023-03-16

    申请号：US17502056

    申请日：2021-10-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Chien-Liang Wu ,  Wen-Kai Lin ,  Te-Wei Yeh ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

    IPC: G11C17/16 ,  G11C16/10

    Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

    Magnetoresistive random access memory
    70.
    发明授权
    Magnetoresistive random access memory 有权

    公开(公告)号：US11569295B2

    公开(公告)日：2023-01-31

    申请号：US16924169

    申请日：2020-07-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

    IPC: H01L27/22 ,  G11C7/18 ,  H01L43/02

    Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Patent Agency Ranking