-
公开(公告)号：US07709313B2
公开(公告)日：2010-05-04
申请号：US11160999
申请日：2005-07-19
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译： 一种双栅极CMOS结构的制造方法和器件。 该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。 隔离结构在第一板和第二板之间。
-
公开(公告)号：US07681628B2
公开(公告)日：2010-03-23
申请号：US11402400
申请日：2006-04-12
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
摘要翻译： 本发明提供对FinFET SRAM单元中的上拉pFET的背栅极偏置的动态控制。 根据本发明的方法包括向SRAM单元中的至少一个晶体管的背栅提供偏置电压，并且基于操作模式（例如，读取，半选择，写入，待机）动态地控制偏置电压， 的SRAM单元。
-
公开(公告)号：US20080195983A1
公开(公告)日：2008-08-14
申请号：US11673824
申请日：2007-02-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5068 , G06F2217/16
摘要： A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base model. The re-fitting algorithm removes any discrepancy between the base model and the stress model as the stress model is applied to the data set obtained from a dimension-scaling macro. Stress offsets for dimension-scaling macro devices are calculated to fit the measured values of the model parameters for the same devices. The process of fitting the model parameters to the data set from the dimension-scaling macro calculates constant, linear, and quadratic coefficients for the model parameters, which are employed to increase the accuracy of the model parameters and of the compact model used in circuit simulations and optimization.
摘要翻译： 提高紧凑型模型中模型参数精度的计算方法使用方法和算法通过将应力模型重新拟合到生成基本模型的数据集来自主统一地匹配独立开发的基础和应力模型。 随着应力模型应用于从尺寸缩放宏获取的数据集，重新拟合算法消除了基本模型和应力模型之间的任何差异。 计算尺寸缩放宏设备的应力偏移量，以适应相同设备的模型参数的测量值。 将模型参数从维度缩放宏拟合到数据集的过程计算模型参数的常数，线性和二次系数，这些系数用于提高模型参数的精度和电路模拟中使用的紧凑模型 和优化。
-
公开(公告)号：US07375000B2
公开(公告)日：2008-05-20
申请号：US11161911
申请日：2005-08-22
IPC分类号： H01L21/20
CPC分类号： H01L29/8605 , H01L27/016 , H01L27/0802 , H01L29/66166
摘要： A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.
摘要翻译： 半导体电阻器，制造电阻器的方法和制造包括电阻器的IC的方法。 掩埋阱形成在绝缘体上硅（SOI）晶片的硅衬底中。 在埋井中形成至少一个沟槽。 电阻器沿着沟槽的侧壁形成，并且在多个沟槽形成支柱的情况下，通过用成角度的植入物掺杂侧壁，在沟槽之间的支柱中形成电阻器。 如果有的话，在沟槽和支柱的相对两端形成电阻触点到掩埋井。
-
公开(公告)号：US20080016477A1
公开(公告)日：2008-01-17
申请号：US11457174
申请日：2006-07-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/31816 , G01R31/318357
摘要： A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.
摘要翻译： 在逻辑电路中对软错误进行建模的方法使用在设备的源极和漏极处插入的两个单独的电流源来模拟由例如α粒子撞击引起的单个事件不正常（SEU）。 在nfet实现中，电流从源极或漏极流向器件的主体。 具有已知幅度的电流波形在电流源处被注入，同时模拟逻辑电路的操作，并且根据模拟操作确定逻辑电路的状态。 可以独立调整电流波形的幅度。 模拟器监视设备的状态，并在转换发生时创建日志条目。 逻辑电路中的其他器件可以重复该过程以提供电路对软错误的敏感性的整体表征。
-
公开(公告)号：US07265005B2
公开(公告)日：2007-09-04
申请号：US11265464
申请日：2005-11-02
IPC分类号： H01L21/338
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/42384 , H01L29/66795 , H01L2029/7858
摘要： A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.
摘要翻译： 形成双栅极鳍型场效应晶体管（FinFET）结构的方法在绝缘体上形成硅散热片，并以与鳍片成角度的方式形成栅极导体。 栅极导体横向地形成在鳍片的中心部分附近并且越过其中心部分。 栅极导体被平坦化，使得栅极导体分离成由鳍分开的不同的栅极导体部分。 这些栅极导体部分包括前门和后门。 前门和后门沿着结构交替，使得每个鳍具有一侧的前门和相对侧上的后门。 然后，前栅极布线形成于前栅极，并且后栅极布线形成于后栅极。
-
公开(公告)号：US07198990B2
公开(公告)日：2007-04-03
申请号：US11137811
申请日：2005-05-24
IPC分类号： H01L21/335
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。 栅极通过栅极电介质耦合到沟道封套。 示例性材料是Si和Si x Ge 1-x x，其中78
-
公开(公告)号：US07102181B1
公开(公告)日：2006-09-05
申请号：US10907971
申请日：2005-04-22
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/42384 , H01L29/66795 , H01L2029/7858
摘要： A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.
-
公开(公告)号：US06844609B2
公开(公告)日：2005-01-18
申请号：US10278431
申请日：2002-10-23
IPC分类号： H01L23/525 , H01L29/00 , H01L21/44
CPC分类号： H01L23/5252 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。
-
公开(公告)号：US06498056B1
公开(公告)日：2002-12-24
申请号：US09702406
申请日：2000-10-31
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。
-
-
-
-
-
-
-
-
-
搜索结果
74 条记录 (耗时 0.028 秒)
