公开(公告)号：US20050086405A1

公开(公告)日：2005-04-21

申请号：US10680615

申请日：2003-10-06

申请人： Grant Kobayashi ,  Barnes Cooper

发明人： Grant Kobayashi ,  Barnes Cooper

IPC分类号： G06F1/32 ,  G06F9/46 ,  G06F12/02 ,  G06F13/24

CPC分类号： G06F12/0284 ,  G06F9/5016 ,  G06F15/16

摘要： A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received, a first processor checks the state of a second processor, which may be done by checking a storage medium storing values representative of the second processor's state. The first processor handles the SMI or waits for the second processor dependent on the state of the second processor. Furthermore, system management memory is allocated where a first system management memory space assigned to a first processor overlaps a second system management memory space assigned to a second processor, leaving first and second non-overlapping region.

摘要翻译： 这里描述了用于优化多处理器同步和分配系统管理存储器空间的方法和装置。 当接收到系统管理中断（SMI）时，第一处理器检查第二处理器的状态，其可以通过检查存储表示第二处理器状态的值的存储介质来完成。 第一个处理器处理SMI或等待第二个处理器取决于第二个处理器的状态。 此外，分配给第一处理器的第一系统管理存储器空间与分配给第二处理器的第二系统管理存储器空间重叠的系统管理存储器被分配，留下第一和第二非重叠区域。

公开(公告)号：US06823240B2

公开(公告)日：2004-11-23

申请号：US10020848

申请日：2001-12-12

申请人： Barnes Cooper

发明人： Barnes Cooper

IPC分类号： G05D2300

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A processor's performance state may be adjusted based on processor temperature. On transitions to a lower performance state due to the processor getting hotter, the processor's frequency is reduced prior to reducing the processor voltage. Thus, the processor's performance, as seen by the operating system, is reduced immediately. Conversely, on transitions to a higher performance state, due to the processor cooling down, the processor's frequency is not increased until the voltage is changed to a higher level. An interrupt event may be generated anytime the processor's phase locked loop relocks at a new frequency level. Thus, when the interrupt fires, the operating system can read the processor's performance state. As a result, interrupts are not generated that would cause processor performance to lag the interrupt event.

公开(公告)号：US06711526B2

公开(公告)日：2004-03-23

申请号：US09750676

申请日：2000-12-29

申请人： Barnes Cooper

发明人： Barnes Cooper

IPC分类号： H04B138

CPC分类号： G06F11/3423

摘要： The utilization of a central processing unit during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the central processing unit. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval.

摘要翻译： 通过测量在中央处理单元时钟信号在中央处理单元的处理器核心内有效的采样时间间隔内的时间量度来确定采样时间间隔期间的中央处理单元的利用率。 使用施加到处理器核心的中央处理单元时钟信号的周期数和中央处理单元时钟信号的周期来确定时间量。 然后利用率可以用时间量与总时间间隔的比来表示。

公开(公告)号：US06701272B2

公开(公告)日：2004-03-02

申请号：US09820863

申请日：2001-03-30

申请人： Barnes Cooper ,  David A. Wyatt ,  Terry M. Fletcher ,  Matt King

发明人： Barnes Cooper ,  David A. Wyatt ,  Terry M. Fletcher ,  Matt King

IPC分类号： G05D2300

CPC分类号： G06F1/206 ,  Y02D10/16

摘要： A method and apparatus are provided for obtaining throttle settings of a system, such as a chipset. A first bandwidth may be applied to a first area (or interface) of the system and a temperature of the first area may be sensed using a thermal sensor. The bandwidth passing through this first area may be increased or decreased based on the sensed temperature to obtain an ideal or optimized setting.

摘要翻译： 提供了一种用于获得诸如芯片组的系统的节流设置的方法和装置。 可以将第一带宽施加到系统的第一区域（或接口），并且可以使用热传感器来感测第一区域的温度。 可以基于所感测的温度来增加或减少通过该第一区域的带宽以获得理想或优化的设置。

公开(公告)号：US20160252942A1

公开(公告)日：2016-09-01

申请号：US14633438

申请日：2015-02-27

申请人： Ankush Varma ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  Krishnakanth V. Sistla ,  James G. Hermerding, II

发明人： Ankush Varma ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  Krishnakanth V. Sistla ,  James G. Hermerding, II

IPC分类号： G06F1/26 ,  G06F1/20 ,  G06F1/32

CPC分类号： G06F1/263 ,  G06F1/206 ,  G06F1/3212 ,  G06F1/324 ,  G06F15/00 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/174

摘要： In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，系统包括：多个计算节点，用于耦合在机架中; 第一共享电源，用于向所述多个计算节点提供基线功率电平; 以及辅助电源，用于在比基线功率电平更高的功率电平的操作期间向多个计算节点中的一个或多个提供电力。 描述和要求保护其他实施例。

公开(公告)号：US20150170315A1

公开(公告)日：2015-06-18

申请号：US14108442

申请日：2013-12-17

申请人： Eric C. Samson ,  Barnes Cooper

发明人： Eric C. Samson ,  Barnes Cooper

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： A system on a chip may include a central processing unit and a graphics processing unit. Based on a user specified target frame rate, it is determined whether a previous processor frame duration for either both of said central and graphics processing unit is too long. It so, at least one of the processors' idle times is decreased. In some embodiments, the frame rate is accessed only if the system on a chip is power limited. In some embodiments, the start of work on the graphics processing unit may be locked to a benchmark such as a v-sync signal or a completion of work on the graphics processor.

摘要翻译： 芯片上的系统可以包括中央处理单元和图形处理单元。 基于用户指定的目标帧速率，确定所述中央处理单元和图形处理单元两者的先前处理器帧持续时间是否过长。 因此，至少有一个处理器的空闲时间减少。 在一些实施例中，仅当芯片上的系统被功率限制时才访问帧速率。 在一些实施例中，图形处理单元上的开始工作可以被锁定到诸如v同步信号或图形处理器上的完成工作之类的基准。

公开(公告)号：US20140189391A1

公开(公告)日：2014-07-03

申请号：US13730625

申请日：2012-12-28

申请人： Jaya L. Jeyaseelan ,  Linda Weyhing ,  Rajeev Nalawadi ,  Barnes Cooper ,  Suraj Varma ,  Nevo Idan ,  David Poisner

发明人： Jaya L. Jeyaseelan ,  Linda Weyhing ,  Rajeev Nalawadi ,  Barnes Cooper ,  Suraj Varma ,  Nevo Idan ,  David Poisner

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  Y02D10/171

摘要： In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.

摘要翻译： 在本文描述的至少一个实施例中，提供了一种装置，其可以包括用于如果软件等待时间容差寄存器模式是活动的，则用于在软件等待时间寄存器中传送连接到平台的设备的等待时间容限值的装置。 该装置还可以包括用于在主机控制器处于活动状态时从硬件等待时间寄存器传送等待时间容差值的装置。 延迟容限值可以发送到电源管理控制器。 更具体的示例可以包括用于在软件延迟容限寄存器模式不活动且主机控制器不活动的情况下从软件延迟寄存器传送延迟容限值的装置。 该装置还可以包括用于使用BIOS /平台驱动器在设备的软件延迟寄存器中映射资源空间的装置。 可以使用高级配置和电源接口设备描述来实现映射。

公开(公告)号：US20140189198A1

公开(公告)日：2014-07-03

申请号：US13730575

申请日：2012-12-28

申请人： Faraz A. Siddiqi ,  Francis R. Corrado ,  Barnes Cooper

发明人： Faraz A. Siddiqi ,  Francis R. Corrado ,  Barnes Cooper

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0638 ,  G06F12/0871 ,  G06F2212/1028 ,  Y02D10/13

摘要： Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented in hardware, the logic to: dynamically allocate at least a first portion of a nonvolatile memory; in response to a command to enter the apparatus into a standby state, the logic to store at least a portion of a context data from a volatile memory to the dynamically allocated first portion of the nonvolatile memory; and in response to a resumption of operation of the apparatus, the logic to copy at least the portion of the context data from the first portion of the nonvolatile memory to the volatile memory, and to reclaim the first portion of the nonvolatile memory for dynamic allocation.

摘要翻译： 快速平台休眠和恢复计算系统的内存分配。 装置的实施例包括至少部分地以硬件方式实现的逻辑，用于：动态地分配非易失性存储器的第一部分的逻辑; 响应于将设备进入待机状态的命令，将从易失性存储器的上下文数据的至少一部分存储到非易失性存储器的动态分配的第一部分的逻辑; 并且响应于所述装置的恢复操作，将所述上下文数据的至少一部分从所述非易失性存储器的第一部分复制到所述易失性存储器的逻辑，以及回收用于动态分配的所述非易失性存储器的所述第一部分 。

公开(公告)号：US20140173306A1

公开(公告)日：2014-06-19

申请号：US13719296

申请日：2012-12-19

申请人： Barnes Cooper ,  Faraz Siddiqi ,  Justin Perrenoud ,  Ping She ,  Claes Olsson ,  Assar Badri ,  Benjamin Clark

发明人： Barnes Cooper ,  Faraz Siddiqi ,  Justin Perrenoud ,  Ping She ,  Claes Olsson ,  Assar Badri ,  Benjamin Clark

IPC分类号： G06F1/32

CPC分类号： G06F1/3268 ,  G06F1/3221 ,  Y02D10/154

摘要： Particular embodiments described herein can offer a method that includes receiving storage operation information that is to indicate one or more storage drive operations, receiving storage independent power information, determining, by a processor, a performance profile based at least in part on the storage operation information and the storage independent power information, and causing a setting of at least one power management directive that is to correspond with the performance profile.

摘要翻译： 本文描述的特定实施例可以提供一种方法，其包括接收用于指示一个或多个存储驱动操作的存储操作信息，接收存储独立功率信息，至少部分地基于存储操作信息由处理器确定性能简档 以及与存储无关的功率信息，并且使得至少一个与所述性能简档相对应的功率管理指令的设置。

公开(公告)号：US20110302626A1

公开(公告)日：2011-12-08

申请号：US13213353

申请日：2011-08-19

申请人： Seh W. Kwa ,  Robert Gough ,  Neil Songer ,  Jaya L. Jeyaseelan ,  Barnes Cooper ,  Nilesh V. Shah

发明人： Seh W. Kwa ,  Robert Gough ,  Neil Songer ,  Jaya L. Jeyaseelan ,  Barnes Cooper ,  Nilesh V. Shah

IPC分类号： H04L29/06

CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/329 ,  Y02D10/24

摘要： In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.