公开(公告)号：US08084822B2

公开(公告)日：2011-12-27

申请号：US12570384

申请日：2009-09-30

申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

IPC分类号： H01L29/66

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.

摘要翻译： Fin-FET和制造鳍式FET的方法。 所述方法包括：在半导体衬底的顶表面上提供包括氧化硅层的衬底，在氧化硅层的顶表面上的加强层和在加强层的顶表面上的单晶硅层; 从单晶硅层形成翅片; 在翅片的通道区域的翅片和相对侧上形成源极和漏极; 在所述沟道区域中的所述鳍片的至少一个表面上形成栅极电介质层; 以及在所述栅极电介质层上形成栅电极。

公开(公告)号：US20110073951A1

公开(公告)日：2011-03-31

申请号：US12570384

申请日：2009-09-30

申请人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

发明人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.

摘要翻译： Fin-FET和制造鳍式FET的方法。 所述方法包括：在半导体衬底的顶表面上提供包括氧化硅层的衬底，在氧化硅层的顶表面上的加强层和在加强层的顶表面上的单晶硅层; 从单晶硅层形成翅片; 在翅片的通道区域的翅片和相对侧上形成源极和漏极; 在所述沟道区域中的所述鳍片的至少一个表面上形成栅极电介质层; 以及在所述栅极电介质层上形成栅电极。

公开(公告)号：US20100246076A1

公开(公告)日：2010-09-30

申请号：US12632015

申请日：2009-12-07

申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Mujahid Muhammad

发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Mujahid Muhammad

IPC分类号： H02H9/00 ,  G06F17/50

CPC分类号： H01L27/0251 ,  G06F17/5045

摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

摘要翻译： 提供了一种用于电力过应力（EOS）保护的半导体电路。 半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。 连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。 特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。 可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

公开(公告)号：US20090268359A1

公开(公告)日：2009-10-29

申请号：US12109820

申请日：2008-04-25

申请人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li

发明人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) and electrical overstress (EOS) events includes a resistor/capacitor (RC) triggering device configured between a pair of power rails; a silicon controlled rectifier (SCR) triggered by the RC triggering device during an ESD event, wherein the SCR, when activated, acts as a power rail voltage clamp; and a field effect transistor (FET) coupled between the RC triggering device and the SCR, wherein the FET serves as an integrated part of the RC triggering device that triggers the SCR during the ESD event; and wherein the FET also operates in a snapback mode to trigger the SCR during an EOS event that is slower in comparison to the ESD event such that the EOS event would not otherwise cause triggering of the SCR via the RC triggering device itself.

摘要翻译： 用于保护集成电路免受静电放电（ESD）和电过载（EOS）事件的装置包括：在一对电源轨之间配置的电阻/电容器（RC）触发装置; 在ESD事件期间由RC触发装置触发的可控硅整流器（SCR），其中所述SCR在被激活时用作电力轨道电压钳位; 以及耦合在RC触发装置和SCR之间的场效应晶体管（FET），其中所述FET用作在ESD事件期间触发SCR的RC触发装置的集成部分; 并且其中所述FET还以快速恢复模式操作以在与ESD事件相比较慢的EOS事件期间触发SCR，使得EOS事件不会通过RC触发装置本身引起触发SCR。

公开(公告)号：US20090026492A1

公开(公告)日：2009-01-29

申请号：US11782800

申请日：2007-07-25

申请人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Dimitrios K. Kontos ,  Mujahid Muhammad

发明人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Dimitrios K. Kontos ,  Mujahid Muhammad

IPC分类号： H01L29/72

CPC分类号： H01L29/7436 ,  H01L27/0262

摘要： The components of a silicon controlled rectifier, which are a p-doped anode, an n-well middle region, a p-well middle region, and an n-doped cathode, are formed along sidewalls and a bottom surface of a shallow trench isolation structure. The p-doped anode and the n-doped cathode are formed directly underneath a top surface of a silicon substrate. A trigger mechanism that provides an instantaneous turn-on current to latch the silicon controlled rectifier to an on-state is also provided. The trigger mechanism provides a temporary surge in the voltage of the p-doped middle region, causing the instantaneous turn-on current to flow from the p-doped middle region to the n-doped cathode. Combined with the proximity of the p-doped anode to the n-doped cathode, the trigger mechanism provides a fast turn on and a short low resistance current path for the electrostatic discharge protection circuit.

摘要翻译： 作为p型掺杂阳极，n阱中间区域，p阱中间区域和n掺杂阴极的可控硅整流器的部件沿着浅沟槽隔离层的侧壁和底面形成 结构体。 p掺杂阳极和n掺杂阴极直接形成在硅衬底的顶表面下方。 还提供了提供瞬时导通电流以将可控硅整流器锁定到导通状态的触发机构。 触发机制提供p掺杂中间区域的电压的暂时浪涌，导致瞬时导通电流从p掺杂的中间区域流到n掺杂的阴极。 结合p掺杂阳极与n掺杂阴极的接近，触发机制为静电放电保护电路提供快速导通和短路电阻电流路径。

公开(公告)号：US08373956B2

公开(公告)日：2013-02-12

申请号：US12943980

申请日：2010-11-11

申请人： Michel J. Abou-Khalil ,  Kiran V. Chatty ,  Chee Kwang Quek ,  Robert J. Gauthier, Jr. ,  Nathaniel Peachey

发明人： Michel J. Abou-Khalil ,  Kiran V. Chatty ,  Chee Kwang Quek ,  Robert J. Gauthier, Jr. ,  Nathaniel Peachey

IPC分类号： H02H9/00 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC分类号： H02H9/046

摘要： A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.

摘要翻译： 一种用于静电放电（ESD）保护的电路和方法。 ESD保护电路包括：连接在第一电压轨和第二电压轨之间的硅控制整流器（SCR）; 在第一电压轨和p沟道场效应晶体管（PFET）的源极之间沿正向传导方向串联连接的一个或多个二极管; 连接到SCR的PFET的漏极通过电流触发装置连接到地; 以及连接到PFET的栅极的控制电路。

公开(公告)号：US08363367B2

公开(公告)日：2013-01-29

申请号：US12632015

申请日：2009-12-07

申请人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

发明人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  G06F17/5045

摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

摘要翻译： 提供了一种用于电力过应力（EOS）保护的半导体电路。 半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。 连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。 特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。 可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

公开(公告)号：US20120250195A1

公开(公告)日：2012-10-04

申请号：US13076625

申请日：2011-03-31

申请人： Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

发明人： Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.

摘要翻译： ESD功率钳位电路及ESD保护方法。 ESD功率钳位电路包括：耦合到电阻/电容（RC）网络的功率钳位装置，RC网络包括作为RC网络的电容元件的电容器和被配置为可变的一个或多个结场效应晶体管（JFET） 电阻器作为RC网络的电阻元件。

公开(公告)号：US20100181621A1

公开(公告)日：2010-07-22

申请号：US12355889

申请日：2009-01-19

申请人： Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Mujahid Muhammad

发明人： Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Mujahid Muhammad

IPC分类号： H01L27/102 ,  G06F17/50 ,  H02H9/00 ,  H01L21/62

CPC分类号： H01L27/0266

摘要： An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure.

摘要翻译： 集成电路，形成集成电路的设计结构和方法，其包括耦合到I / O信号焊盘的信号焊盘ESD和耦合到源VDD的电源ESD。 信号垫ESD和电源ESD集成在单个ESD结构中。

公开(公告)号：US20090278201A1

公开(公告)日：2009-11-12

申请号：US12116237

申请日：2008-05-07

申请人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

发明人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/78654 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78603

摘要： Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.

摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 场效应晶体管包括：半导体衬底; 衬底上的氧化硅层; 氧化硅层上的加强层; 加强层上的单晶硅层; 在硅层的沟道区的相对侧上的源极和漏极; 沟道区上的栅极电极和栅电极和沟道区之间的栅极电介质。