公开(公告)号：US08234451B1

公开(公告)日：2012-07-31

申请号：US13190035

申请日：2011-07-25

申请人： Anant Agarwal ,  Ian R. Bratt ,  Matthew Mattina

发明人： Anant Agarwal ,  Ian R. Bratt ,  Matthew Mattina

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817

摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

摘要翻译： 多核处理器包括多个高速缓存存储器和多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联。 至少一些高速缓存存储器中的每一个被配置为保持高速缓冲存储器的至少一部分，其中每个高速缓存行被动态地管理为相关联的处理器核心的本地或在多个处理器核心之间共享。

公开(公告)号：US08155113B1

公开(公告)日：2012-04-10

申请号：US11302961

申请日：2005-12-13

申请人： Anant Agarwal

发明人： Anant Agarwal

IPC分类号： H04L12/50 ,  H04Q11/00 ,  G06F13/00 ,  G06F15/00 ,  G06F15/76

CPC分类号： G06F15/8007 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3851 ,  G06F15/17381 ,  G06F15/7867 ,  H03K19/177 ,  H03K19/17704 ,  Y02D10/12 ,  Y02D10/13

摘要： An integrated circuit includes a plurality of tiles, and a plurality of interface modules coupled to the switches of a subset of the tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles. At least some of the interface modules are configured to multiplex data from one or more parallel communication links of the switch to an multiplexed communication link having reduced parallelization, and mediate between a network protocol of the switch and a communication protocol of the multiplexed communication link.

摘要翻译： 集成电路包括多个瓦片，以及耦合到瓦片子集的开关的多个接口模块。 每个瓦片包括处理器和包括切换电路的开关，该切换电路用于通过数据路径将数据从其他瓦片转发到处理器以及其他瓦片的切换。 至少一些接口模块被配置为将来自交换机的一个或多个并行通信链路的数据复用到具有减少的并行化的复用的通信链路，并且在交换机的网络协议和多路通信链路的通信协议之间进行中介。

公开(公告)号：US20120018737A1

公开(公告)日：2012-01-26

申请号：US12840583

申请日：2010-07-21

申请人： Qingchun Zhang ,  Anant Agarwal

发明人： Qingchun Zhang ,  Anant Agarwal

IPC分类号： H01L29/24 ,  H01L29/744 ,  H01L21/332

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/66363 ,  H01L29/744

摘要： Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated.

摘要翻译： 公开了补偿半导体晶片上的不均匀蚀刻的电子器件结构及其制造方法。 在一个实施例中，电子设备包括多个层，包括由期望的半导体材料形成的第一掺杂类型的半导体基底层，也由所需半导体材料形成的基底层上的半导体缓冲层，以及一个或多个 在缓冲层上具有更多的第二掺杂类型的接触层。 蚀刻一个或多个接触层以形成电子器件的第二接触区域。 缓冲层在制造电子器件期间减少对半导体基底层的损伤。 优选地，选择半导体缓冲层的厚度以补偿由于在其上制造电子器件的半导体晶片上的不均匀蚀刻而导致的过蚀刻。

公开(公告)号：US08078832B1

公开(公告)日：2011-12-13

申请号：US12128073

申请日：2008-05-28

申请人： Anant Agarwal ,  David Wentzlaff

发明人： Anant Agarwal ,  David Wentzlaff

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/45 ,  G06F9/46

CPC分类号： G06F15/76 ,  G06F8/52 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3897 ,  G06F9/455 ,  G06F9/45504 ,  G06F9/5061 ,  G06F15/7867 ,  G06F2209/5011

摘要： An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.

公开(公告)号：US20110250737A1

公开(公告)日：2011-10-13

申请号：US13167806

申请日：2011-06-24

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

公开(公告)号：US07804504B1

公开(公告)日：2010-09-28

申请号：US11302962

申请日：2005-12-13

申请人： Anant Agarwal

发明人： Anant Agarwal

IPC分类号： G06F15/80 ,  G06F13/14 ,  G06F17/50 ,  H03K17/693 ,  H03K19/00

CPC分类号： G06F15/8007 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3851 ,  G06F15/17381 ,  G06F15/7867 ,  H03K19/177 ,  H03K19/17704 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for manufacturing an integrated circuit is described. The integrated circuit comprises a plurality of tiles, each tile comprising a processor and a switch coupled to neighboring tiles to form a network of tiles. The method includes identifying at least one tile that includes a fault, and forming data paths through one or more tiles to preserve communication in the network.

摘要翻译： 对集成电路的制造方法进行说明。 集成电路包括多个瓦片，每个瓦片包括处理器和耦合到相邻瓦片的开关以形成瓦片网络。 该方法包括识别包括故障的至少一个瓦片，以及通过一个或多个瓦片形成数据路径以保持网络中的通信。

公开(公告)号：US07795691B2

公开(公告)日：2010-09-14

申请号：US12019690

申请日：2008-01-25

申请人： Qingchun Zhang ,  Sarah Haney ,  Anant Agarwal

发明人： Qingchun Zhang ,  Sarah Haney ,  Anant Agarwal

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7396

摘要： The invention is a device for controlling conduction across a semiconductor body with a P type channel layer between active semiconductor regions of the device and the controlling gate contact. The device, often a MOSFET or an IGBT, includes at least one source, well, and drift region. The P type channel layer may be divided into sections, or divided regions, that have been doped to exhibit N type conductivity. By dividing the channel layer into regions of different conductivity, the channel layer allows better control over the threshold voltage that regulates current through the device. Accordingly, one of the divided regions in the channel layer is a threshold voltage regulating region. The threshold-voltage regulating region maintains its original P type conductivity and is available in the transistor for a gate voltage to invert a conductive zone therein. The conductive zone becomes the voltage regulated conductive channel within the device.

摘要翻译： 本发明是一种用于通过在器件的有源半导体区域和控制栅极接触之间的P型沟道层来控制半导体本体导通的装置。 该器件通常是MOSFET或IGBT，包括至少一个源极，阱和漂移区。 P型沟道层可以被分成已被掺杂以显示N型导电性的部分或分割区域。 通过将沟道层分成不同导电率的区域，通道层可以更好地控制调节通过器件的电流的阈值电压。 因此，沟道层中的一个分割区域是阈值电压调节区域。 阈值电压调节区域保持其原始P型电导率，并且在晶体管中可用于栅极电压以反转其中的导电区域。 导电区域成为设备内的电压调节导电通道。

公开(公告)号：US07734894B1

公开(公告)日：2010-06-08

申请号：US12110871

申请日：2008-04-28

申请人： David Wentzlaff ,  Anant Agarwal

发明人： David Wentzlaff ,  Anant Agarwal

IPC分类号： G06F15/00

CPC分类号： G06F15/16

摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and coupling circuitry configured to couple data resulting from processing an instruction from at least one of the streams of instructions to the storage module and to the switch.

摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括包括存储模块的处理器，其中所述处理器被配置为处理多个指令流，开关包括切换电路，以将从其他瓦片到数据路径接收的数据转发到处理器，以及转发其他瓦片 从处理器接收的数据到其他瓦片的切换器，以及耦合电路，其被配置为将从指令流中的至少一个处理指令得到的数据耦合到存储模块和交换机。

公开(公告)号：US20100090271A1

公开(公告)日：2010-04-15

申请号：US12560729

申请日：2009-09-16

申请人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

发明人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7803 ,  H01L21/0465 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/861

摘要： A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse biase the p-n junction between the drift region and the body region.

摘要翻译： 半导体器件包括具有第一导电类型的漂移层和与漂移层相邻的体区。 身体区域具有与第一导电类型相反的第二导电类型，并与漂移层形成p-n结。 该器件还包括在体区中具有第一导电类型的接触器区域和从接触器区域延伸穿过体区的分流通道区域到漂移层。 分流通道区域具有第一导电类型。 该装置还包括与主体区域和接触器区域电接触的第一端子和与漂移层电接触的第二端子。 分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于 内置电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区和体区之间的pn结的电压不导通。

公开(公告)号：US07622949B1

公开(公告)日：2009-11-24

申请号：US12130462

申请日：2008-05-30

申请人： Anant Agarwal

发明人： Anant Agarwal

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： G06F15/8007 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3851 ,  G06F15/17381 ,  G06F15/7867 ,  H03K19/177 ,  H03K19/17704 ,  Y02D10/12 ,  Y02D10/13

摘要： An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

摘要翻译： 集成电路包括多个瓦片。 每个瓦片包括处理器，开关，其包括用于将数据从其他瓦片转发到处理器的数据路径以及其他瓦片的切换的切换电路;以及存储指令流的开关存储器，所述指令流能够独立地对于相应输出端口 开关。