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    SiC devices with high blocking voltage terminated by a negative bevel
    1.
    发明授权
    SiC devices with high blocking voltage terminated by a negative bevel 有权
    具有高阻断电压的SiC器件由负斜角端接

    公开(公告)号：US09337268B2

    公开(公告)日：2016-05-10

    申请号：US13108366

    申请日：2011-05-16

    申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L29/16

    CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

    摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

    摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。

    Electronic device structure with a semiconductor ledge layer for surface passivation
    2.
    发明授权
    Electronic device structure with a semiconductor ledge layer for surface passivation 有权
    具有用于表面钝化的半导体凸缘层的电子器件结构

    公开(公告)号：US08809904B2

    公开(公告)日：2014-08-19

    申请号：US12843113

    申请日：2010-07-26

    申请人： Qingchun Zhang ,  Anant Agarwal

    发明人： Qingchun Zhang ,  Anant Agarwal

    IPC分类号： H01L29/36

    CPC分类号： H01L29/66378 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66234 ,  H01L29/66363 ,  H01L29/744

    摘要： Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

    摘要翻译： 公开了包括用于表面钝化的半导体凸缘层的电子器件结构及其制造方法。 在一个实施例中，电子器件包括具有交替掺杂类型的期望半导体材料的多个半导体层。 半导体层包括第一掺杂类型的基极层，其包括形成电子器件的第一接触区域的高度掺杂的阱和在基底层上的第二掺杂类型的一个或多个接触层，其被蚀刻以形成第二掺杂阱 电子设备的接触区域。 一个或多个接触层的蚀刻在基层的表面上引起显着的晶体损伤，并因此导致界面电荷。 为了钝化基底层的表面，半导体材料的半导体凸缘层至少在基底层的表面上外延生长。

    Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same
    3.
    发明授权
    Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same 有权
    包括具有排列成岛的掺杂区域的肖特基二极管的半导体器件及其制造方法

    公开(公告)号：US08330244B2

    公开(公告)日：2012-12-11

    申请号：US12492670

    申请日：2009-06-26

    申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07

    CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

    摘要： A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.

    摘要翻译： 根据一些实施例的半导体器件包括具有第一导电类型的半导体层和限定半导体器件的有源区的表面。 多个间隔开的第一掺杂区域被布置在有源区域内。 多个第一掺杂区域具有与第一导电类型相反的第二导电类型，具有第一掺杂剂浓度，并且在有源区内限定半导体层的多个暴露部分。 多个第一掺杂区域在半导体层中被布置为岛状。 半导体层中的第二掺杂区域具有第二导电类型并且具有大于第一掺杂剂浓度的第二掺杂剂浓度。

    Transistor with A-Face Conductive Channel and Trench Protecting Well Region
    5.
    发明申请
    Transistor with A-Face Conductive Channel and Trench Protecting Well Region 有权
    具有A面导电沟道和沟槽保护区的晶体管

    公开(公告)号：US20090146154A1

    公开(公告)日：2009-06-11

    申请号：US11952447

    申请日：2007-12-07

    申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

    发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

    IPC分类号： H01L29/24 ,  H01L29/78 ,  H01L29/74 ,  H01L21/04

    CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

    摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

    摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

    Semiconductor devices including Schottky diodes with controlled breakdown and methods of fabricating same
    6.
    发明申请
    Semiconductor devices including Schottky diodes with controlled breakdown and methods of fabricating same 有权
    包括具有受控击穿的肖特基二极管的半导体器件及其制造方法

    公开(公告)号：US20080029838A1

    公开(公告)日：2008-02-07

    申请号：US11496842

    申请日：2006-08-01

    申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    IPC分类号： H01L29/47

    CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

    摘要： A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel with the Schottky junction. The first p-n junction is configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to thereby limit reverse leakage current through the Schottky junction. The first p-n junction is further configured such that punch-through of the first p-n junction occurs at a lower voltage than a breakdown voltage of the Schottky junction when the Schottky junction is reverse biased.

    摘要翻译： 半导体器件包括具有第一导电类型的半导体层，半导体层上的金属接触并与半导体层形成肖特基结，以及半导体层中的半导体区域。 半导体区域和半导体层与肖特基结并联形成第一p-n结。 第一p-n结被配置为当肖特基结被反向偏置时在与肖特基结相邻的半导体层中产生耗尽区，从而限制通过肖特基结的反向漏电流。 第一p-n结进一步配置成使得当肖特基结被反向偏置时，第一p-n结的穿通以比肖特基结的击穿电压低的电压发生。

    TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION
    9.
    发明申请
    TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION 审中-公开
    具有导通通道和保护区域的晶体管

    公开(公告)号：US20120235164A1

    公开(公告)日：2012-09-20

    申请号：US13482311

    申请日：2012-05-29

    申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

    发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

    IPC分类号： H01L29/16 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

    摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

    摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

    ELECTRONIC DEVICE STRUCTURE WITH A SEMICONDUCTOR LEDGE LAYER FOR SURFACE PASSIVATION
    10.
    发明申请
    ELECTRONIC DEVICE STRUCTURE WITH A SEMICONDUCTOR LEDGE LAYER FOR SURFACE PASSIVATION 有权
    具有半导体LED层的电子器件结构用于表面钝化

    公开(公告)号：US20120018738A1

    公开(公告)日：2012-01-26

    申请号：US12843113

    申请日：2010-07-26

    申请人： Qingchun Zhang ,  Anant Agarwal

    发明人： Qingchun Zhang ,  Anant Agarwal

    IPC分类号： H01L29/24 ,  H01L29/744 ,  H01L29/74 ,  H01L29/72 ,  H01L21/332 ,  H01L21/331

    CPC分类号： H01L29/66378 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66234 ,  H01L29/66363 ,  H01L29/744

    摘要： Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

    摘要翻译： 公开了包括用于表面钝化的半导体凸缘层的电子器件结构及其制造方法。 在一个实施例中，电子器件包括具有交替掺杂类型的期望半导体材料的多个半导体层。 半导体层包括第一掺杂类型的基极层，其包括形成电子器件的第一接触区域的高度掺杂的阱和在基底层上的第二掺杂类型的一个或多个接触层，其被蚀刻以形成第二掺杂阱 电子设备的接触区域。 一个或多个接触层的蚀刻在基层的表面上引起显着的晶体损伤，并因此导致界面电荷。 为了钝化基底层的表面，半导体材料的半导体凸缘层至少在基底层的表面上外延生长。