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    Production of semiconductor integrated circuit
    63.
    发明授权
    Production of semiconductor integrated circuit 失效
    生产半导体集成电路

    公开(公告)号：US06740901B2

    公开(公告)日：2004-05-25

    申请号：US10307354

    申请日：2002-12-02

    申请人： Hiroshi Miki ,  Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Tomoyuki Hamada

    发明人： Hiroshi Miki ,  Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Tomoyuki Hamada

    IPC分类号： H01L27108

    CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L28/91

    摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

    摘要翻译： 一种半导体集成电路，其中存储电容器具有增加的电容和减小的漏电流。 存储电容器通过以下步骤形成：形成其上形成有半球形硅晶体的多晶硅底电极; 在低于550℃的温度下在所述底部电极的表面上进行等离子体氮化，从而形成膜厚度小于1.5nm的氮化硅膜; 并沉积无定形钽五氧化物膜，然后使所述无定形五氧化钽结晶。 氮化硅膜具有改善的抗氧化性，并且还具有减小的漏电流。 结果，多晶硅底部电极变得耐氧化，并且存储电容器增加电容并且减小漏电流。

    Semiconductor integrated circuits and fabricating method thereof
    64.
    发明授权
    Semiconductor integrated circuits and fabricating method thereof 失效
    半导体集成电路及其制造方法

    公开(公告)号：US06693792B2

    公开(公告)日：2004-02-17

    申请号：US10411282

    申请日：2003-04-11

    申请人： Yasuhiro Shimamoto ,  Hiroshi Miki ,  Masahiko Hiratani

    发明人： Yasuhiro Shimamoto ,  Hiroshi Miki ,  Masahiko Hiratani

    IPC分类号： H01G406

    CPC分类号： H01L28/40 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/56 ,  H01L28/84 ,  H01L28/90

    摘要： A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.

    摘要翻译： 具有3.0nm以下的等效厚度的电容器，具有足够的静电容量和较小的漏电流，通过堆叠具有2.5nm或更大的物理厚度的界面膜21来构成，用于抑制隧道漏电流和高 介电膜22包括在下电极19上的五氧化钽，20，包括粗糙多晶硅膜，界面膜21包括通过LPCVD法形成的氮化物膜，例如Al2O3，Al2O3和SiO2的混合相，ZrSiO4，HfSiO4， Y2O3和SiO2的混合相以及La2O3和SiO2的混合相。

    Semiconductor device having a capacitor structure including a self-alignment deposition preventing film
    66.
    发明授权
    Semiconductor device having a capacitor structure including a self-alignment deposition preventing film 有权
    具有包括自对准防沉积膜的电容器结构的半导体器件

    公开(公告)号：US06483143B2

    公开(公告)日：2002-11-19

    申请号：US09810401

    申请日：2001-03-19

    申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

    发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

    IPC分类号： H01L27108

    CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

    摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

    摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。 在预定温度下在下电极和防沉积膜上形成电介质膜。 即使暴露在用于形成电介质膜的预定温度下，下电极的材料也不会导通。 上电极进一步形成在电介质膜上。 上下电极和氧化物介质膜一起构成存储单元的电容器。