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公开(公告)号：US06509246B2
公开(公告)日：2003-01-21
申请号：US09877207
申请日：2001-06-11
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.
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公开(公告)号：US06583023B2
公开(公告)日：2003-06-24
申请号：US10118887
申请日：2002-04-10
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/31604 , H01L27/10814 , H01L28/56 , H01L28/84 , H01L28/90
摘要： A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.
摘要翻译： 具有3.0nm以下的等效厚度的电容器，具有足够的静电容量和较小的漏电流，通过堆叠具有2.5nm或更大的物理厚度的界面膜21来构成，用于抑制隧道漏电流和高 介电膜22包括在下电极19上的五氧化钽，20，包括粗糙多晶硅膜，界面膜21包括通过LPCVD法形成的氮化物膜，例如Al2O3，Al2O3和SiO2的混合相，ZrSiO4，HfSiO4， Y2O3和SiO2的混合相以及La2O3和SiO2的混合相。
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公开(公告)号：US06740901B2
公开(公告)日：2004-05-25
申请号：US10307354
申请日：2002-12-02
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.
摘要翻译： 一种半导体集成电路，其中存储电容器具有增加的电容和减小的漏电流。 存储电容器通过以下步骤形成：形成其上形成有半球形硅晶体的多晶硅底电极; 在低于550℃的温度下在所述底部电极的表面上进行等离子体氮化，从而形成膜厚度小于1.5nm的氮化硅膜; 并沉积无定形钽五氧化物膜，然后使所述无定形五氧化钽结晶。 氮化硅膜具有改善的抗氧化性，并且还具有减小的漏电流。 结果，多晶硅底部电极变得耐氧化，并且存储电容器增加电容并且减小漏电流。
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公开(公告)号：US06693792B2
公开(公告)日：2004-02-17
申请号：US10411282
申请日：2003-04-11
IPC分类号： H01G406
CPC分类号： H01L28/40 , H01L21/31604 , H01L27/10814 , H01L28/56 , H01L28/84 , H01L28/90
摘要： A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.
摘要翻译： 具有3.0nm以下的等效厚度的电容器，具有足够的静电容量和较小的漏电流，通过堆叠具有2.5nm或更大的物理厚度的界面膜21来构成，用于抑制隧道漏电流和高 介电膜22包括在下电极19上的五氧化钽，20，包括粗糙多晶硅膜，界面膜21包括通过LPCVD法形成的氮化物膜，例如Al2O3，Al2O3和SiO2的混合相，ZrSiO4，HfSiO4， Y2O3和SiO2的混合相以及La2O3和SiO2的混合相。
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公开(公告)号：US06787451B2
公开(公告)日：2004-09-07
申请号：US10216792
申请日：2002-08-13
IPC分类号： H01L2972
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02178 , H01L21/02266 , H01L21/02323 , H01L21/02329 , H01L21/02337 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/3143 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545
摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.
摘要翻译： 在具有SiO 2当量厚度为2nm以上的栅极绝缘膜的FET的制造方法中，能够将漏电流抑制到{部分（与现有的SiO 2膜相比为1/100以下）的SiO 2膜为0.5nm 以上的Si基板（多晶硅栅极）和高介电绝缘膜之间的边界处形成，并且使SiO 2膜的形成温度高于后续工序中的源极 - 漏极活化热处理温度，因此 可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低引起的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。
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公开(公告)号：US06989304B1
公开(公告)日：2006-01-24
申请号：US10297811
申请日：2000-08-11
IPC分类号： H01L21/8242
CPC分类号： C23C14/046 , C23C14/165 , C23C16/18 , H01L21/7687 , H01L27/10814 , H01L27/10852 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/91
摘要： In the method of manufacturing a semiconductor device according to this invention, when an interlayer insulating film is fabricated such that an opening is cylindrical and low-pressure and long-throw sputtering is used for forming a lower ruthenium electrode, a ruthenium film can be deposited on the side wall of a deep hole. Further, after removing the ruthenium film deposited on the upper surface of the interlayer insulating film, a dielectric material comprising, for example, a tantalum pentoxide film is deposited. Successively, an upper ruthenium electrode is deposited using, for example, Ru(EtCp)2 as a starting material and by chemical vapor deposition of conveying the starting material by bubbling. The upper ruthenium electrode can be formed with good coverage by using conditions that the deposition rate of the ruthenium film depends on the formation temperature (reaction controlling condition). This invention can provide a fine concave type capacitor having a ruthenium electrode.
摘要翻译： 在根据本发明的半导体器件的制造方法中，当制造使得开口为圆柱形的层间绝缘膜并且使用低压和长距离溅射来形成下部钌电极时，可以沉积钌膜 在一个深孔的侧壁上。 此外，在除去沉积在层间绝缘膜的上表面上的钌膜之后，沉积包括例如五氧化二钽膜的电介质材料。 接着，使用例如Ru（EtCp）2 N 2作为起始材料并通过化学气相沉积，通过鼓泡输送起始材料来沉积上钌电极。 通过使用钌膜的沉积速率取决于形成温度（反应控制条件）的条件，可以形成具有良好覆盖度的上钌电极。 本发明可以提供一种具有钌电极的细凹型电容器。
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公开(公告)号：US06521494B2
公开(公告)日：2003-02-18
申请号：US10211569
申请日：2002-08-05
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.
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8.发明授权公开(公告)号：US06503791B2
公开(公告)日：2003-01-07
申请号：US09767706
申请日：2001-01-24
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film.
摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。
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公开(公告)号：US07259058B2
公开(公告)日：2007-08-21
申请号：US10020314
申请日：2001-12-18
申请人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Satoshi Yamamoto , Toshihide Nabatame , Toshio Ando , Hiroshi Sakuma , Shinpei Iijima
发明人： Yasuhiro Shimamoto , Masahiko Hiratani , Yuichi Matsui , Satoshi Yamamoto , Toshihide Nabatame , Toshio Ando , Hiroshi Sakuma , Shinpei Iijima
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , C23C16/18 , H01L21/28556 , H01L21/28568 , H01L28/55 , H01L28/91
摘要： A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.
摘要翻译： 通过化学气相沉积法形成氧气污染少，热稳定性高的钌电极。 在使用有机钌化合物作为前体的化学气相沉积方法中，氧化气体的引入限于当前体供应时，并且允许反应在低氧分压下发生。 因此，可以形成氧含量低的钌膜。 此外，在形成钌膜之后，进行不低于形成温度的退火，由此形成热稳定性高的钌膜。
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公开(公告)号：US07119407B2
公开(公告)日：2006-10-10
申请号：US10900430
申请日：2004-07-28
IPC分类号： H01L29/72
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02178 , H01L21/02266 , H01L21/02323 , H01L21/02329 , H01L21/02337 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/3143 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545
摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.
摘要翻译： 在具有SiO 2等效厚度为2nm以上的栅极绝缘膜的FET的制造方法中，与现有的SiO 2相比，能够将漏电流抑制到1/100以下， 在Si衬底（多晶硅栅极）和高介电绝缘膜之间的边界处形成0.5nm或更大的SiO 2 SiO 2膜，并且形成 SiO 2膜比后续步骤中的源极 - 漏极活化热处理温度高。 因此，可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低导致的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。
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