公开(公告)号：US20110049454A1

公开(公告)日：2011-03-03

申请号：US12305890

申请日：2006-06-23

申请人： Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

发明人： Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

IPC分类号： H01L45/00

CPC分类号： H01L45/1675 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

摘要： In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.

摘要翻译： 在相变存储器中，界面层插入硫族化物材料层和插塞之间。 界面层被布置成不覆盖插塞状电极的整个界面。 当塞子形成在比硫族化物层的上部时，积分度增加。 通过使用氧化物靶进行溅射而形成界面层，或者通过使用金属靶进行溅射而形成金属膜，然后在氧自由基，氧等离子体等的氧化气氛中氧化金属膜。

公开(公告)号：US20070285983A1

公开(公告)日：2007-12-13

申请号：US11790590

申请日：2007-04-26

申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

公开(公告)号：US20070176219A1

公开(公告)日：2007-08-02

申请号：US11612922

申请日：2006-12-19

申请人： Taro OSABE ,  Takashi Ishigaki ,  Yoshitaka Sasago

发明人： Taro OSABE ,  Takashi Ishigaki ,  Yoshitaka Sasago

IPC分类号： H01L29/94

CPC分类号： H01L27/11553 ,  G11C11/16 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of floating gates are formed on a principal surface of a semiconductor substrate that constitutes a nonvolatile semiconductor memory device through a first gate dielectric film. An auxiliary gate formed on the principal surface of the semiconductor substrate through a third gate dielectric film is formed on one adjacent side of the floating gates. A groove is formed on the other adjacent side of the floating gate, and an n-type diffusion layer is formed on a bottom side of the groove. A data line of the nonvolatile semiconductor memory device is constituted by an inversion layer formed on the principal surface of the semiconductor substrate to be opposed to an auxiliary gate by applying desired voltage to the auxiliary gate, and the n-type diffusion layer.

摘要翻译： 多个浮置栅极通过第一栅极电介质膜形成在构成非易失性半导体存储器件的半导体衬底的主表面上。 通过第三栅极电介质膜形成在半导体衬底的主表面上的辅助栅极形成在浮动栅极的一个相邻侧上。 在浮置栅极的另一个相邻侧上形成有沟槽，并且在槽的底侧上形成n型扩散层。 非易失性半导体存储器件的数据线由通过向辅助栅极和n型扩散层施加所需电压而形成在半导体衬底的主表面上以与辅助栅极相对的反型层构成。

公开(公告)号：US20110235386A1

公开(公告)日：2011-09-29

申请号：US13154113

申请日：2011-06-06

申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

IPC分类号： G11C5/02

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

公开(公告)号：US20090014770A1

公开(公告)日：2009-01-15

申请号：US12169789

申请日：2008-07-09

申请人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

发明人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

IPC分类号： H01L29/00

CPC分类号： H01L45/145 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2213/11 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

摘要： A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

摘要翻译： 通过采用能够高精度地控制固体电解质中的离子的运动的装置结构，通过提高具有记录或切换功能的半导体器件的性能，可以以低成本实现多层次三维结构的高集成度的技术。 器件的半导体元件如下形成; 分别在垂直（z轴）方向上分开设置的一对电极之间分别沉积两层或更多层，然后在这些电极之间施加脉冲电压以形成导电路径。 路径的电阻值根据信息信号而变化。 此外，在导电路径的中间部分形成区域。 该区域用于累积改善路径的导电性的分量，从而使电阻值（速率）能够当前响应于信息信号。 更优选地，电极也应至少形成在x轴方向或y轴方向上，以向电极施加控制电压。

公开(公告)号：US07323741B2

公开(公告)日：2008-01-29

申请号：US10998630

申请日：2004-11-30

申请人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

发明人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/7885 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328

摘要： A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.

摘要翻译： 能够使用反转层作为布线的能够进行高速编程的低成本半导体非易失性存储器件以及该器件的制造方法。 半导体存储器件包括在源极和漏极区域之间并与之平行的位置处的辅助电极，并且与相互平行形成的源极区域和漏极区域没有位置重叠; 其中用于热电子源注入的辅助电极用作编程（写入）的辅助电极; 并且在读取操作期间，在辅助电极下形成的反型层用作源极区域或漏极区域。

公开(公告)号：US20070228455A1

公开(公告)日：2007-10-04

申请号：US11619561

申请日：2007-01-03

申请人： Yoshitaka Sasago ,  Tomoyuki Ishii ,  Toshiyuki Mine

发明人： Yoshitaka Sasago ,  Tomoyuki Ishii ,  Toshiyuki Mine

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： In the memory array area of a semiconductor substrate, memory cells of a NAND flash memory are arranged in a matrix in the row direction and the column direction. A plurality of memory cells arranged in the row direction are mutually isolated by device isolation trenches having a thin strip planar shape extending in the column direction. The diameter of the device isolation trenches in the row direction at the bottom portion thereof is larger than that near the surface.

摘要翻译： 在半导体衬底的存储器阵列区域中，NAND闪速存储器的存储单元被排列成行方向和列方向的矩阵。 沿行方向布置的多个存储单元通过在列方向上延伸的薄的带状平面形状的器件隔离沟相互隔离。 器件隔离沟槽在其底部的行方向上的直径大于靠近表面的直径。

公开(公告)号：US20050127429A1

公开(公告)日：2005-06-16

申请号：US10998630

申请日：2004-11-30

申请人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

发明人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328

摘要： A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.

摘要翻译： 能够使用反转层作为布线的能够进行高速编程的低成本半导体非易失性存储器件以及该器件的制造方法。 半导体存储器件包括在源极和漏极区域之间并与之平行的位置处的辅助电极，并且与相互平行形成的源极区域和漏极区域没有位置重叠; 其中用于热电子源注入的辅助电极用作编程（写入）的辅助电极; 并且在读取操作期间，在辅助电极下形成的反型层用作源极区域或漏极区域。

公开(公告)号：US20150155479A1

公开(公告)日：2015-06-04

申请号：US14405721

申请日：2012-06-04

申请人： Yoshitaka Sasago

发明人： Yoshitaka Sasago

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/144

摘要： The purpose of the present invention is to provide a semiconductor storage device, which has small resistance in the ON state, and a small leak current in the OFF state, and which has a small-sized select transistor used therein. In this semiconductor storage device, a channel of a first select transistor that selects a memory cell array is electrically connected to each of the adjacent memory cell arrays (see FIG. 1).

摘要翻译： 本发明的目的是提供一种半导体存储装置，其在导通状态下具有小的电阻，并且在关闭状态下具有小的漏电流，并且其中使用了小尺寸的选择晶体管。 在该半导体存储装置中，选择存储单元阵列的第一选择晶体管的沟道电连接到各相邻的存储单元阵列（参照图1）。

公开(公告)号：US07829930B2

公开(公告)日：2010-11-09

申请号：US12169789

申请日：2008-07-09

申请人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

发明人： Motoyasu Terao ,  Hideyuki Matsuoka ,  Naohiko Irie ,  Yoshitaka Sasago ,  Riichiro Takemura ,  Norikatsu Takaura

IPC分类号： H01L27/108

CPC分类号： H01L45/145 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2213/11 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

摘要： A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

摘要翻译： 通过采用能够高精度地控制固体电解质中的离子的运动的装置结构，通过提高具有记录或切换功能的半导体器件的性能，可以以低成本实现多层次三维结构的高集成度的技术。 器件的半导体元件如下形成; 分别在垂直（z轴）方向上分开设置的一对电极之间分别沉积两层或更多层，然后在这些电极之间施加脉冲电压以形成导电路径。 路径的电阻值根据信息信号而变化。 此外，在导电路径的中间部分形成区域。 该区域用于累积改善路径的导电性的分量，从而使电阻值（速率）能够当前响应于信息信号。 更优选地，电极也应至少形成在x轴方向或y轴方向上，以向电极施加控制电压。