公开(公告)号：US20050237783A1

公开(公告)日：2005-10-27

申请号：US11128038

申请日：2005-05-12

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  H01L29/792 ,  G11C11/22

CPC分类号： G11C16/0466 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

公开(公告)号：US06903406B2

公开(公告)日：2005-06-07

申请号：US10346957

申请日：2003-01-17

申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

公开(公告)号：US06894924B2

公开(公告)日：2005-05-17

申请号：US10133684

申请日：2002-04-25

申请人： Jung-Dal Choi ,  Chang-Hyun Lee

发明人： Jung-Dal Choi ,  Chang-Hyun Lee

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

摘要： An operation method of programming, erasing, and reading a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device having a tunnel oxide layer thicker than 20 Å is provided. A program operation of the method is accomplished by applying a program voltage higher than 0 volts and a ground voltage to a gate electrode and a channel region of a selected SONOS cell transistor, respectively. Also, an erasing operation is accomplished by applying a ground voltage and a first erase voltage lower than 0 volts to a bulk region and a gate electrode of a selected SONOS cell transistor, respectively, and by applying a second erasure voltage to either a drain region or a source region of the selected SONOS cell transistor. The second erase voltage is a ground voltage or a positive voltage. In addition, a read operation is accomplished using either a backward read mode or a forward read mode. Thus, it is possible to remarkably improve a bake retention characteristic, which is sensitive to a thickness of the tunnel oxide layer.

摘要翻译： 提供了一种编程，擦除和读取具有大于20埃的隧道氧化物层的氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储器件的操作方法。 该方法的程序操作通过分别向所选择的SONOS单元晶体管的栅电极和沟道区施加高于0伏的编程电压和接地电压来实现。 此外，擦除操作是通过分别对所选择的SONOS单元晶体管的体区域和栅电极施加接地电压和低于0伏特的第一擦除电压来实现的，并且通过向漏极区域施加第二擦除电压 或所选择的SONOS单元晶体管的源极区域。 第二擦除电压是接地电压或正电压。 此外，使用反向读取模式或正向读取模式来实现读取操作。 因此，可以显着提高对隧道氧化物层的厚度敏感的烘烤保持特性。

公开(公告)号：US06336376B1

公开(公告)日：2002-01-08

申请号：US09419713

申请日：1999-10-14

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： G05G114

CPC分类号： G05G1/32 ,  B60T7/065 ,  Y10T74/20528 ,  Y10T74/2063

摘要： A brake pedal supporting structure designed for a brake pedal of a car having a pedal arm coupled with a mounting bracket attached to a dash panel and a cowl panel to rotate via an actuating rod and a hinge point of a brake booster, wherein pedal arm pushing preventing means is fixed at the rear portion of the pedal arm to face a predetermined interval of the total length of the pedal arm including the hinge point to prevent the pedal arm from being pushed to the rear by the brake booster which will be pushed toward the inside of the car room at the time of a head-on colliding car crash, thereby keeping the pedal arm from being pushed toward the rear of the chassis or enabling the lower portion of the pedal arm to rotate to the front of the chassis to rule out an impact given by the pedal arm onto the driver's lower body and reduce the possibility of the injury at the time of the head-on colliding car crash.

摘要翻译： 一种制动踏板支撑结构，其设计用于汽车的制动踏板，该制动踏板具有踏板臂，该踏板臂与连接到仪表板上的安装支架连接，并且前罩板经由致动杆和制动助力器的铰接点旋转，其中踏板臂推动 防止装置固定在踏板臂的后部以面对包括铰链点的踏板臂的总长度的预定间隔，以防止踏板臂被制动助力器推向后方，该制动助力器将被推向 在碰撞碰撞时，汽车内部的内部，从而保持踏板臂不被推向底盘的后部，或使踏板臂的下部旋转到底盘的前面以规定 将踏板臂施加到驾驶员的下身上，并减少在碰撞碰撞时发生伤害的可能性。

公开(公告)号：US10134753B2

公开(公告)日：2018-11-20

申请号：US15455900

申请日：2017-03-10

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/792

摘要： According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other.

公开(公告)号：US09640549B2

公开(公告)日：2017-05-02

申请号：US14534181

申请日：2014-11-06

申请人： Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

发明人： Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11548 ,  H01L27/11575 ,  G11C8/14 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11582 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

公开(公告)号：US09443596B2

公开(公告)日：2016-09-13

申请号：US14192544

申请日：2014-02-27

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3427

摘要： A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor. The voltage generator generates a program voltage, a first pass voltage, and a second pass voltage. A first boost channel voltage applied when programming an outermost memory cell from among the memory cells of each of non-selected cell strings of the cell strings is lower than a second boost channel voltage applied when programming one of remaining memory cells except for the outermost memory cell. The non-volatile memory device prevents programming disturb caused by hot carrier injection.

摘要翻译： 非易失性存储器件包括存储单元阵列和电压发生器。 存储单元阵列具有多个单元串，其中多个存储单元串联连接在串选择晶体管和接地选择晶体管之间。 电压发生器产生编程电压，第一通过电压和第二通过电压。 当从单元串的未选择单元串中的每一个的存储器单元中编程最外层存储单元时施加的第一升压通道电压低于在编程除最外存储器之外的剩余存储单元之一时所应用的第二升压通道电压 细胞。 非易失性存储器件防止由热载流子注入引起的编程干扰。

公开(公告)号：US20140264549A1

公开(公告)日：2014-09-18

申请号：US14191568

申请日：2014-02-27

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66833 ,  H01L29/7926

摘要： A vertical memory device includes a substrate, a column of vertical channels on the substrate and spaced apart along a direction parallel to the substrate, respective charge storage structures on sidewalls of respective ones of the vertical channels and gate electrodes vertically spaced along the charge storage structures. The vertical memory device further includes an isolation pattern disposed adjacent the column of vertical channels and including vertical extension portions extending parallel to the vertical channels and connection portions extending between adjacent ones of the vertical extension portions.

摘要翻译： 垂直存储器件包括衬底，衬底上的垂直通道列，并沿着平行于衬底的方向间隔开，相应的垂直通道的侧壁上的电荷存储结构和沿着电荷存储结构垂直间隔开的栅电极 。 垂直存储装置还包括邻近垂直通道列布置的隔离图案，并且包括平行于垂直通道延伸的垂直延伸部分和在相邻的垂直延伸部分之间延伸的连接部分。

公开(公告)号：US20140264548A1

公开(公告)日：2014-09-18

申请号：US14176332

申请日：2014-02-10

申请人： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

发明人： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/76224 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/7889

摘要： A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

摘要翻译： 存储器件可以包括在衬底上的多个半导体图案，其包括以第一杂质浓度掺杂的多个第一杂质区域，在与多个半导体图案接触并且以第二杂质掺杂的衬底的部分处的多个第二杂质区域 浓度，多个半导体图案上的多个沟道图案，多个栅极结构，在与多个栅极结构的端部相邻的基板的部分处的多个第三杂质区域，以及多个第四杂质区域 在第二和第三杂质区之间和相邻的第二杂质区之间的衬底的部分。 可以在可以低于第一和第二杂质浓度的第三杂质浓度下掺杂多个第四杂质区域。

公开(公告)号：US08427883B2

公开(公告)日：2013-04-23

申请号：US12980788

申请日：2010-12-29

申请人： Dae-Suk Kim ,  Chang-Hyun Lee

发明人： Dae-Suk Kim ,  Chang-Hyun Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/109 ,  G11C29/46

摘要： A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.

摘要翻译： 设置电路包括：响应于测试信号选择预定码和外部码之一的选择单元;以及设置信息生成单元，用于响应于由选择单元选择的代码生成设置信息。