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146 条记录 (耗时 0.035 秒)

    Integrated circuit package and fabricating method thereof
    61.
    发明授权
    Integrated circuit package and fabricating method thereof 有权
    集成电路封装及其制造方法

    公开(公告)号：US07829388B2

    公开(公告)日：2010-11-09

    申请号：US12694239

    申请日：2010-01-26

    申请人： Chin-Yung Chen ,  Chia-Hung Hsu ,  William Wang ,  Chung-Cheng Chou

    发明人： Chin-Yung Chen ,  Chia-Hung Hsu ,  William Wang ,  Chung-Cheng Chou

    IPC分类号： H01L21/00

    CPC分类号： H01L23/3735 ,  H01L23/3677 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.

    摘要翻译： 本发明公开了一种集成电路封装。 集成电路封装包括具有第一表面和与其相对的第二表面的基板以及从第一表面到第二表面穿过基板的第一孔。 多个导电线设置在基板的第二表面的一部分上。 半导体芯片设置在衬底的第二表面上方，其中在半导体芯片和衬底之间形成腔室。 多个接合焊盘设置在半导体芯片的朝向衬底的第二表面的一侧上，其中至少一个接合焊盘电连接到多条导线之一。 第一散热层设置在第一孔中并延伸到腔室中。 还提供了一种用于制造集成电路封装的方法。

    OPTICAL TOUCH APPARATUS AND OPERATING METHOD THEREOF
    62.
    发明申请
    OPTICAL TOUCH APPARATUS AND OPERATING METHOD THEREOF 审中-公开
    光触摸装置及其操作方法

    公开(公告)号：US20100259507A1

    公开(公告)日：2010-10-14

    申请号：US12718643

    申请日：2010-03-05

    申请人： Meng-Shin Yen ,  William Wang ,  Chung-Cheng Chou

    发明人： Meng-Shin Yen ,  William Wang ,  Chung-Cheng Chou

    IPC分类号： G06F3/042

    CPC分类号： G06F3/0421

    摘要： An optical touch apparatus and operating method thereof are disclosed. The optical touch apparatus comprises an optical module, a light sensing module, and a processing module. The optical module and the light sensing module are set at a first side and an opposite second side of a surface of the optical touch apparatus respectively. The optical module receives a light source and uniformly emits a plurality of lights. When at least one of the plurality of lights is blocked by an object above the surface, the light sensing module generates a sensing result based on the condition of receiving the plurality of lights. The processing module determines a touch point location corresponding to the object on the surface based on the sensing result.

    摘要翻译： 公开了一种光学触摸装置及其操作方法。 光学触摸装置包括光学模块，光感测模块和处理模块。 光学模块和感光模块分别设置在光学触摸装置的表面的第一侧和相对的第二侧。 光学模块接收光源并均匀地发射多个光。 当多个光中的至少一个光被表面上方的物体阻挡时，光感测模块基于接收多个光的条件产生感测结果。 处理模块基于感测结果确定与表面上的对象相对应的触摸点位置。

    MICROINJECTION APPARATUS WITH THERMOCHROMIC INDICATOR
    67.
    发明申请
    MICROINJECTION APPARATUS WITH THERMOCHROMIC INDICATOR 审中-公开
    微电子显微照相装置

    公开(公告)号：US20070091133A1

    公开(公告)日：2007-04-26

    申请号：US11536148

    申请日：2006-09-28

    申请人： Chung-Cheng Chou ,  William Wang ,  Chen Peng

    发明人： Chung-Cheng Chou ,  William Wang ,  Chen Peng

    IPC分类号： B41J29/38

    CPC分类号： B41J29/393 ,  B41J2/14137 ,  B41J2/14153 ,  B41J2/1606

    摘要： The invention provides a microinjection apparatus for a fluid. The microinjection apparatus comprises a substrate, a manifold, at least one fluid chamber, and at least one thermal sensing film. The manifold is formed on the substrate for containing the fluid therein. The at least one fluid chamber is also formed on the substrate and in communication with the manifold. Furthermore, the fluid chamber has a respective orifice and a respective heater disposed adjacent to the orifice. In addition, the thermal sensing film corresponds to the fluid chamber and is formed on a surface adjacent to the orifice. It should be noticed that the thermal sensing film has a respective color changeable in response to a heat generated during operation of the corresponding heater.

    摘要翻译： 本发明提供一种用于流体的显微注射装置。 显微注射装置包括基板，歧管，至少一个流体室和至少一个热敏膜。 歧管形成在基板上，用于在其中容纳流体。 至少一个流体室也形成在基板上并与歧管连通。 此外，流体室具有相应的孔口和邻近孔口设置的相应加热器。 此外，热敏膜对应于流体室，并且形成在与孔口相邻的表面上。 应该注意的是，热敏膜具有响应于相应加热器的操作期间产生的热而可以变化的相应颜色。

    SRAM write assist apparatus
    68.
    发明授权
    SRAM write assist apparatus 有权
    SRAM写入辅助装置

    公开(公告)号：US08724420B2

    公开(公告)日：2014-05-13

    申请号：US13105382

    申请日：2011-05-11

    申请人： Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

    发明人： Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

    IPC分类号： G11C11/413

    CPC分类号： G11C11/419 ,  G11C11/41 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

    摘要： An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.

    摘要翻译： SRAM写入辅助装置包括定时器单元和分压器。 分压器单元被配置为将电压电位分压到较低电平。 在写入操作中，分压器的输出连接到存储单元。 定时器单元被配置为产生具有与施加到存储芯片的电压电位成反比的宽度的脉冲。 此外，定时器单元控制将来自分压器的输出的较低电压施加到存储单元的周期。 此外，可以使用外部电平和定时可编程信号来进一步调整分压器的比例和来自定时器单元的脉冲宽度。 通过采用SRAM写入辅助装置，存储器芯片可以执行可靠且快速的写入操作。

    Internal clock gating apparatus
    69.
    发明授权
    Internal clock gating apparatus 有权
    内部时钟选通装置

    公开(公告)号：US08575965B2

    公开(公告)日：2013-11-05

    申请号：US13118060

    申请日：2011-05-27

    申请人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

    发明人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

    IPC分类号： H03K19/096

    CPC分类号： G06F1/3287 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/171

    摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.

    摘要翻译： 内部时钟选通装置包括静态逻辑块和多米诺逻辑块。 静态逻辑块被配置为接收时钟信号和时钟使能信号。 多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。 静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。 另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。 此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。

    Internal Clock Gating Apparatus
    70.
    发明申请
    Internal Clock Gating Apparatus 有权
    内部时钟门控器

    公开(公告)号：US20120299622A1

    公开(公告)日：2012-11-29

    申请号：US13118060

    申请日：2011-05-27

    申请人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

    发明人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yangsyu Lin ,  Hsiao Wen Lu

    IPC分类号： H03K19/096

    CPC分类号： G06F1/3287 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/171

    摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.

    摘要翻译： 内部时钟选通装置包括静态逻辑块和多米诺逻辑块。 静态逻辑块被配置为接收时钟信号和时钟使能信号。 多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。 静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。 另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。 此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。