公开(公告)号：US20070116374A1

公开(公告)日：2007-05-24

申请号：US11652720

申请日：2007-01-11

Applicant: Alvin Despain

Inventor： Alvin Despain

IPC: G06K9/40

CPC classification number: H03H21/0029

Abstract: A computationally efficient, adaptive multistage Wiener filter employs two modules, a linear filter module that operates at the input data rate and an update module that operates at a plurality of rates but performs many calculations at only the update rate. This filter is especially useful when the channel conditions vary slowly so that the filter's update rate can be considerably less than the input data rate. Separating the calculations, preferably performing appropriate calculations at different rates and preferably substituting scalar operations for vector operations can provide improved computational efficiency while maintaining high levels of performance.

公开(公告)号：US07181085B1

公开(公告)日：2007-02-20

申请号：US10348670

申请日：2003-01-21

Applicant: Alvin M. Despain

Inventor： Alvin M. Despain

IPC: G06K9/40 ,  G06K9/00

CPC classification number: H03H21/0029

Abstract: A computationally efficient, adaptive multistage Wiener filter employs two modules, a linear filter module that operates at the input data rate and an update module that operates at a plurality of rates but performs many calculations at only the update rate. This filter is especially useful when the channel conditions vary slowly so that the filter's update rate can be considerably less than the input data rate. Separating the calculations, preferably performing appropriate calculations at different rates and preferably substituting scalar operations for vector operations can provide improved computational efficiency while maintaining high levels of performance.

Abstract translation: 计算效率高的自适应多级维纳滤波器采用两个模块，一个以输入数据速率运行的线性滤波器模块，以及一个以多个速率工作的更新模块，但只在更新速率下进行许多计算。 当信道条件变化较慢时，该滤波器特别有用，因此滤波器的更新速率可以远低于输入数据速率。 分离计算，优选以不同的速率执行适当的计算，并且优选地对标量运算进行矢量运算，可以提供改善的计算效率，同时保持高水平的性能。

公开(公告)号：US07176483B2

公开(公告)日：2007-02-13

申请号：US10753504

申请日：2004-01-07

Applicant: Daniel E. Grupp ,  Daniel J. Connelly

Inventor： Daniel E. Grupp ,  Daniel J. Connelly

IPC: H01L39/00

CPC classification number: H01L29/0895 ,  H01L21/28537 ,  H01L29/45 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/812

Abstract: An electrical junction that includes a semiconductor (e.g., C, Ge, or an Si-based semiconductor), a conductor, and an interface layer disposed therebetween. The interface layer is sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm2, and in some cases a minimum specific contact resistance.

Abstract translation: 包括半导体（例如，C，Ge或Si基半导体），导体和设置在其间的界面层的电连接。 界面层足够厚以消除半导体的费米能级，但足够薄以提供具有小于或等于约1000Ωm2的特定接触电阻的结，并且在一些 情况下具体接触电阻最小。

公开(公告)号：US06891234B1

公开(公告)日：2005-05-10

申请号：US10832576

申请日：2004-04-26

Applicant: Daniel J. Connelly ,  Carl Faulkner ,  Daniel E. Grupp

Inventor： Daniel J. Connelly ,  Carl Faulkner ,  Daniel E. Grupp

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/0847 ,  H01L29/41725 ,  H01L29/4983 ,  H01L29/66643 ,  H01L29/7831

Abstract: An electrical switching device includes a semiconductor having a channel therein which is proximate to at least on channel tap in an extension region and also to a gate. A conductor (e.g., a metal) is disposed proximate to the extension region but is electrically isolated from both the extension region and the gate (e.g., through the use of one or more insulators). The conductor has a workfunction outside of the bandgap of a semiconductor in the extension region and therefore includes a layer of charge in the extension region. The magnitude and polarity of this layer of charge is controlled through selection of the metal, the semiconductor, and the insulator.

Abstract translation: 电开关装置包括其中具有通道的半导体，其在延伸区域中至少接近通道抽头并且还连接到栅极。 导体（例如，金属）设置在延伸区域附近，但与延伸区域和栅极（例如通过使用一个或多个绝缘体）电隔离。 导体在延伸区域中具有在半导体的带隙之外的功函数，因此在延伸区域中包括一层电荷。 通过选择金属，半导体和绝缘体来控制该电荷层的大小和极性。

公开(公告)号：US11043571B2

公开(公告)日：2021-06-22

申请号：US15418360

申请日：2017-01-27

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp ,  Daniel J. Connelly

IPC: H01L29/47 ,  H01L21/285 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/812 ,  H01L23/535 ,  H01L29/06 ,  H01L29/786

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

公开(公告)号：US10388748B2

公开(公告)日：2019-08-20

申请号：US15728002

申请日：2017-10-09

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp ,  Daniel J. Connelly

IPC: H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L29/812 ,  H01L29/16 ,  H01L29/161 ,  H01L29/872 ,  H01L29/80

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

公开(公告)号：US10084091B2

公开(公告)日：2018-09-25

申请号：US15594436

申请日：2017-05-12

Applicant: Acorn Technologies, Inc.

Inventor： Paul A. Clifton ,  R. Stockton Gaines

IPC: H01L31/117 ,  H01L29/78 ,  H01L21/762 ,  H01L29/786 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7849 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/7838 ,  H01L29/7846 ,  H01L29/78603

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

公开(公告)号：US20170034027A1

公开(公告)日：2017-02-02

申请号：US14811507

申请日：2015-07-28

Applicant: Acorn Technologies, Inc.

Inventor： Steven C Thompson ,  Fernando Lopez de Victoria

IPC: H04L12/26 ,  H04L5/00

Abstract: A wireless receiver receives location pilots embedded in received symbols and uses the location pilots to detect the first path for every base station the network has designated for the receiver to use in time of arrival estimation. The receiver preferably applies matching pursuit strategies to offer a robust and reliable identification of a channel impulse response's first path. The receiver may also receive and use estimation pilots as a supplement to the location pilot information in determining time of arrival. The receiver can use metrics characteristic of the channel to improve the robustness and reliability of the identification of a CIR's first path. With the first path identified, the receiver measures the time of arrival for signals from that path and the receiver determines the observed time difference of arrival (OTDOA) to respond to network requests for OTDOA and position determination measurements.

Abstract translation: 无线接收机接收嵌入在接收到的符号中的位置导频，并使用位置导频来检测网络为接收机在到达时间估计中使用的每个基站指定的第一路径。 接收机优选地应用匹配追踪策略来提供信道脉冲响应的第一路径的鲁棒和可靠的识别。 在确定到达时间时，接收机还可以接收和使用估计导频作为位置导频信息的补充。 接收机可以使用信道特征的度量来提高CIR第一条路径的识别的鲁棒性和可靠性。 在识别出第一路径的情况下，接收机测量来自该路径的信号的到达时间，并且接收机确定观察到的到达时间差（OTDOA）以响应OTDOA的网络请求和位置确定测量。

公开(公告)号：US20160308057A1

公开(公告)日：2016-10-20

申请号：US15191369

申请日：2016-06-23

Applicant: Acorn Technologies, Inc.

Inventor： Paul A. Clifton ,  R Stockton Gaines

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7849 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/7838 ,  H01L29/7846 ,  H01L29/78603

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Abstract translation: SOI晶片包含压应力埋层绝缘体结构。 在一个示例中，应力埋层绝缘体（BOX）可以通过形成氧化硅，氮化硅和氧化硅层而形成在主晶片上，使得氮化硅层受到压应力。 晶片接合在应力绝缘体层上提供表面硅层。 本发明的优选实施方案通过将隔离沟槽蚀刻到具有应力BOX结构的优选SOI衬底中来形成MOS晶体管，以在SOI衬底的表面上限定晶体管有源区。 最优选地，沟槽形成得足够深以穿过受压的BOX结构并且进入到衬底的下面的硅部分的一些距离。 覆盖的硅有源区域将由于弹性边缘松弛而产生拉伸应力。

公开(公告)号：US09362376B2

公开(公告)日：2016-06-07

申请号：US14360473

申请日：2012-10-18

Applicant: ACORN TECHNOLOGIES, INC.

Inventor： Walter A Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/04 ,  H01L21/283

CPC classification number: H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Abstract translation: 通过在金属和半导体之间的界面处插入V族或III族原子的单层或者插入由每个单层单层制成的双层来降低金属 - 半导体（IV族）结的特定接触电阻的技术， 或插入多个这样的双层。 所得到的低比电阻金属组IV半导体结可用作包括电子器件（例如，晶体管，二极管等）和光电器件（例如，激光器，太阳能电池，光电检测器等）的半导体器件中的低电阻电极， 和/或作为场效应晶体管（FET）中的金属源极和/或漏极区域（或其一部分）。 III族和V族原子的单层主要是在IV族半导体的表面上形成的化学键合到IV族半导体的表面原子上的原子的有序层。