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    INTEGRATED SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS
    62.
    发明申请
    INTEGRATED SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS 审中-公开

    公开(公告)号：US20200335498A1

    公开(公告)日：2020-10-22

    申请号：US16755817

    申请日：2018-11-21

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

    IPC: H01L27/088 ,  H01L29/78

    Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

    Delay locked loop detection method and system
    63.
    发明授权
    Delay locked loop detection method and system 有权

    公开(公告)号：US10797707B2

    公开(公告)日：2020-10-06

    申请号：US15741448

    申请日：2016-05-10

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Xueyan Wang ,  Ying Yang ,  Jingjia Yu

    IPC: H03L7/081 ,  H03L7/08 ,  H03L7/00

    Abstract: A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testing instrument (500). Also included is a delay locked loop detection method. The system and method mentioned above enable an accurate measurement for the delays of the delay locked loop.

    Method and system for correcting driving amplitude of gyro sensor
    64.
    发明授权
    Method and system for correcting driving amplitude of gyro sensor 有权

    公开(公告)号：US10782148B2

    公开(公告)日：2020-09-22

    申请号：US16673634

    申请日：2019-11-04

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Huagang Wu

    IPC: G01C25/00 ,  G01C19/56 ,  G01C19/5776

    Abstract: A method for correcting the driving amplitude of a gyro sensor, mainly comprises adjusting the size of a driving signal (a preset amplitude value) through feedback of a sensor response amplitude signal (an average amplitude value) in a resonance maintaining time period, so that the response amplitude of the resonance maintaining time period tends to be equal, and a stable resonance amplitude is maintained. Also provided is a system for correcting the driving amplitude of a gyro sensor.

    Lateral insulated-gate bipolar transistor and manufacturing method therefor
    65.
    发明授权
    Lateral insulated-gate bipolar transistor and manufacturing method therefor 有权

    公开(公告)号：US10770572B2

    公开(公告)日：2020-09-08

    申请号：US16311276

    申请日：2017-06-21

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Shukun Qi

    IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/417

    Abstract: A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

    INTEGRATED CIRCUIT CHIP AND MANUFACTURING METHOD THEREFOR, AND GATE DRIVE CIRCUIT
    66.
    发明申请
    INTEGRATED CIRCUIT CHIP AND MANUFACTURING METHOD THEREFOR, AND GATE DRIVE CIRCUIT 审中-公开

    公开(公告)号：US20200258782A1

    公开(公告)日：2020-08-13

    申请号：US16643170

    申请日：2018-08-31

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Lihui GU ,  Sen ZHANG ,  Congming QI

    IPC: H01L21/8249 ,  H01L29/739 ,  H01L29/78 ,  H01L27/06

    Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS device (N1).

    Clock voltage step-up circuit
    67.
    发明授权
    Clock voltage step-up circuit 有权

    公开(公告)号：US10659040B2

    公开(公告)日：2020-05-19

    申请号：US16328402

    申请日：2017-08-22

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Chuan Luo

    IPC: H03K17/06 ,  H03K17/687 ,  H03K5/02

    Abstract: A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped.

    Power on reset circuit
    69.
    发明授权
    Power on reset circuit 有权

    公开(公告)号：US10340912B2

    公开(公告)日：2019-07-02

    申请号：US15731768

    申请日：2015-09-17

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Yun Gao

    IPC: G06F1/24 ,  H03K17/22 ,  G05F3/24 ,  H03K17/687

    Abstract: A power on reset circuit, comprising: a threshold level control circuit (120) configured to set threshold level values of power on reset and power off reset; a capacitor charge and discharge circuit (130) configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and a current bias circuit (110) configured to provide a reference current not varying with a power supply to the threshold level control circuit (120) and the capacitor charge and discharge circuit (130), comprising: a first reference current output terminal connected to the threshold level control circuit (120); a second reference current output terminal connected to the capacitor charge and discharge circuit (130); and a third reference current output terminal connected to the capacitor charge and discharge circuit (130).

    Switch control circuit with booster
    70.
    发明授权
    Switch control circuit with booster 有权

    公开(公告)号：US10236876B2

    公开(公告)日：2019-03-19

    申请号：US15748156

    申请日：2016-05-11

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Chuan Luo

    IPC: H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K17/10 ,  H03K19/0175

    Abstract: A switch control circuit includes: a clock circuit (110) configured to generate a first clock control signal (CLK1) and a second clock control signal (CLK2); a voltage boosting circuit (120) configured to receive the second clock control signal (CLK2) and an operating voltage outputted by the power source (VDD); and boost the operating voltage by a preset value to form a switch control signal (H1) under the control of the second clock control signal (CLK2); and an inverting circuit (130) configured to receive the first clock control signal (CLK1) and the switch control signal (H1), and determine whether or not to output the switch control signal (H1) to the switch circuit according to the first clock control signal (CLK1), so as to control on/off of the switch circuit.

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